Pouya Hashemi received his Ph.D. degree (with honor) in Department of Electrical Engineering and Computer Science at Massachusetts Institute of Technology (MIT) in September 2010 and his B.Sc. and M.Sc. degrees in electrical engineering, both with highest honors, from University of Tehran in 2003 and 2005, respectively.
He is currently a research staff member at IBM research center at Yorktown Heights, NY, with hands on exploratory logic devices (high mobility strained SiGe, Ge, III-V FinFETs/GAA FETs), unconventional high-speed transistors as well as memory devices (STT-MRAM) for advanced technology nodes. In 2010 and 2011, he was a post-doctoral associate at the MIT MTL working on advanced strained-Ge on insulator substrates and top-down fabricated Si/Ge nanowires for high-performance CMOS and SiGe based solar cells. From 2002 to 2005, he was with the Thin-Film Research Laboratories at University of Tehran working on electrical and optical properties of nano-crystalline silicon and fabrication of low temperature Si and Ge thin-film transistors on flexible substrates. In 2005, he joined MIT Microsystems Technology Laboratories where his research was focused on fabrication and investigation of carrier transport in nano-scale strained SOI, SiGe and Ge channel CMOS devices with planar and nanowire architectures. In summer 2009, he was with IBM research and worked on process development of multi-crystalline based Si solar cells.
Dr. Hashemi is the recipient of the 2014 IEEE George E. Smith award in 2015, IBM Ph.D. Fellowship award in 2008, TSMC outstanding research award/commendation in 2010, the Jin-Au Kong Award (Honorable Mention) for best MIT Electrical Engineering Ph.D. Thesis in 2011, and winner of the MIT Microsystems Technology Laboratories Doctoral Dissertation Seminar in Spring 2011. His work has led to near 100 peer-reviewed journals and conferences and over 270 pending or issued US patents. He is also a senior member of IEEE Electron Device Society.