Michael B. Healy has been a Research Staff Member at the IBM Research T.J. Watson Research Center in Yorktown Heights, New York since 2013. Prior to this he was a post-doctoral fellow in the same group. His research interests cover a wide range of topics from low-level processor design to high-level system architecture. Michael's current work focuses heavily on the memory subsystem, where he contributes to the definition of the upcoming DDR5 standard. He also explores the use of 3D stacked memories such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC), as well as novel 3D stacked memories with different design points for bandwidth, latency, and power tradeoffs in novel memory subsystem architectures along with emerging Non-Volatile Memories (NVM). Michael is also a core contributer to IBM's publicly available ControlleR And Memory Simulator (CramSim), which is distributed with Sandia National Laboratory's Structural Simulation Toolkit (SST) on GitHub. Dr. Healy graduated from the Georgia Institute of Technology with B.S., M.S., and Ph.D. degrees in Computer Engineering in 2004, 2006, and 2010, respectively.