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Chip Planner


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VLSI design automation has come a long way, yet early-stage system-level chip planning remains a manual step that relies heavily on experience of architects, instead of a systematic exploration of design spaces. During this step, architects make judgments that have decisive impacts on chip performance, and sub-optimality introduced here is rarely recoverable in later design stages, -- mistakes are costly.

On the other hand, dimensions of design spaces are growing due to 1) heterogeneous architectures, 2) design options from technology scaling, voltage scaling, package co-design, etc., and 3) the need for trade-off analysis with respect to key objectives such as power, temperature, power/current distribution, and reliability. Things are even more complicated for 3D chip designs. Consequently, it has become more and more difficult for chip architects to manually find an optimal design point in these vast design spaces.

The Chip Planner project aims to bridge this gap and greatly improve the productivity of chip design at the early concept phase. The following figure illustrates the Chip Planner environment. It has a front-end that is used for chip architect input and output, plus a back-end which performs various analyses. Currently, the front-end interface is Microsoft Excel spreadsheets, where the chip architect can specify desirable architecture configurations, technology scaling rules, and package material and geometry properties. Built-in VBA (Visual Basic for Applications) macros take the chip architects inputs, set up remote connection to the back-end server, initiate the execution of the tools, wait until the execution completes and transfers results back to the spreadsheets. Once the results are received, they are displayed in a pop-up window as text and/or plots. This process is fully automated. While we chose the spreadsheet as the front-end interface, it can be implemented with other applications such as web-based front-end.

The main functions of the Chip Planner run on the back-end server. It begins with a library of reference designs, -- previous designs with similar functionality but on a different technology. Each reference design includes its physical implementation in OpenAccess format, power estimation reports, etc. The Chip Planner converts these data to XML-based internal database called PAD (Processor Architecture Description). It then extracts units from the reference design library, scales them with respect to target technology, performance and power, and places them using heuristics and architect guidance. It provides power, thermal, electrical and reliability reports back to the spreadsheets, and thereby enables the architect to perform trade-off analysis efficiently. Finally, the Chip Planner creates a netlist of a new design in certain details with data, power, ground and clock pins of the composing units, and passes it on to the implementation stage.

The Chip Planner has been used in several projects and enabled chip architects to explore many more configurations and floorplans with higher accuracy than traditional manual methods. The following figure illustrates a special-purpose server processor in a 3D technology. For this project, the close coupling of system architecture, floorplan and package data has allowed alternative designs to be evaluated in hours, instead of days or weeks which would be required in traditional manual processes. The automatic scaling and user-directed floorplanning, based on detailed placement data derived from reference designs, exposed many subtle issues, which, in a traditional flow, would have surfaced much later in chip integration.