Systems Technology and Microarchitecture
Pipeline SpectroscopyA new method of obtaining, and displaying information on the detailed operation of a pipelined processor has been developed. It allows for the visualization of the costs, and benefits of various processor operations, such as cache misses, trailing edge effects, and prefetching. In particular it allows us to determine when costs overlap, reducing the penalty, or when benefits overlap, reducing their efficacy. This tool is leading to advances in processor design.
Cache Behavior and the Origin of the sqrt(2) RuleA statistical theory of cache operation has been worked out, which shows that cache misses depend on cache size by a negative inverse power law in agreement with observation. The theory shows that this law arises from the temporal dependence of cache references. This understanding leads to an accurate analytical model of cache performance, and to a theory of the optimal memory hierarchy for a processor.
Universal Prefetching StudyThis work provides a robust methodology to analyze the effectiveness of prefetches in the presence of realistic bus bandwidth, and latencies at different levels of the memory hierarchy. A cycle accurate model developed for this work allows exploration of the benefits of any arbitrary prefetch algorithm by suitably setting the timeliness, accuracy, and coverage parameters.
Optimum Pipeline Depth for a MicroprocessorAn analytical theory of the optimal pipeline depth for a microprocessor has been developed and verified with simulations. The theory can give results dependent only on a performance metric or a combined power performance metric. This allows us to readily choose an initial FO4 design point early in the design process, and study the trade-offs inherent in any real design problem.
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