Nianzheng Cao photo Bruce M. Fleischer photo Sudhir Gowda photo
 Shih-Hsien Lo photo Robert A. Philhower photo Phillip J. Restle photo
 Michael R. Scheuermann photoChing Zhou photo Matthew M. Ziegler photo

Research Areas

Group Name

POWER7 (TM) Microprocessor Design


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In February 2010, IBM announced new POWER7™ systems designed to manage the most demanding emerging applications, ranging from smart electrical grids to real-time analytics for financial markets. The systems are built around the POWER7™ microprocessor, a high-performance VLSI chip that includes eight quad-threaded cores, connected at high bandwidth to an on-chip memory subsystem consisting of a private L2-cache (256KB) memory plus a large shared eDRAM (32MB) L3-cache, and with high-speed system links. The microprocessor operates at > 4.0 GHz clock frequency. The POWER7™ microprocessor chip is designed by multi-site teams. The Research team worked on all aspects of VLSI design as well as design tools and methodologies for this chip. Performance exceeding 4GHz is achieved at acceptable power levels using mostly static, custom-designed CMOS circuits for the dataflow. Synthesized logic, implemented using circuit books from a standard cell library, is used for most control circuits. Many innovative power management techniques are employed to achieve high-frequency operation within a given power constraint. The circuits are fabricated in IBM's 45-nm CMOS Silicon-on-Insulator technology with 11 levels of low-k copper wiring.

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Recent Publications:

[1] Dieter Wendel, Ronald Kalla, Robert Cargoni, Joachim Clables,Joshua Friedrich, Roland Frech, James Kahle, Balaram Sinharoy, William Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Saiful Islam, Victor Zyuban, "The Implementation of POWER7TM: A Highly Parallel and Scalable Multi-Core High-End Server Processor," ISSCC 2010 Digest of Technical Papers, pp. 102-103.

[2] James Warnock, Leon Sigal, Dieter Wendel, K Paul Muller,Joshua Friedrich, Victor Zyuban, Ethan Cannon, A.J. KleinOsowski, "POWER7TM Local Clocking and Clocked Storage Elements," ISSCC 2010 Digest of Technical Papers, pp. 178-179.

[3] John Barth, Don Plass, Erik Nelson, Charlie Hwang,Gregory Fredeman, Michael Sperling, Abraham Mathews,William Reohr, Kavita Nair, Nianzheng Cao "A 45nm SOI Embedded DRAM Macro for POWER7TM 32MB On-Chip L3 Cache," ISSCC 2010 Digest of Technical Papers, pp. 342-343.

[4] Juergen Pille, Dieter Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Froehnel, Stefan Buettner, Otto Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles Canada, "A 32kB 2R/1W L1 Data Cache in 45nm SOI Technology for the POWER7TM Processor," ISSCC 2010 Digest of Technical Papers, pp. 344-345.

[5] D. F. Wendel, J. Barth, D. M. Dreps, S. Islam, J. Pille, J. A. Tierno, "IBM POWER7TM processor circuit design," IBM JRD vol. 55, no. 3, paper 6, May/June 2011.

[6] V. Zyuban, J. Friedrich, C. J. Gonzalez, R. Rao, M. D. Brown, M. M. Ziegler, H. Jacobson, S. Islam, S. Chu, P. Kartschoke, G. Fiorenza, M. Boersma, J. A. Culp, "Power optimization methodology for the IBM POWER7 microprocessor," IBM JRD vol. 55, no. 3, paper 7, May/June 2011.

[7] J. Friedrich,R. Puri, U. Brandt, M. Buehler,J. DiLullo, J. Hopkins, M. Hossain, M. Kazda, J. Keinert, Z. M. Kurzum, D. Lamb, A. Lee, F. Musante, J. Noack, P. J. Osler, S. Posluszny, H. Qian, S. Ramji, V. Rao, L. N. Reddy, H. Ren, T. Rosser, B. R. Russell, C. Sze, G. Tellez, "Design methodology for the IBM POWER7 microprocessor," IBM JRD vol. 55, no. 3, paper 9, May/June 2011.