Power Reduction in High-Performance Microprocessors       


 Bruce M. Fleischer photo Sudhir Gowda photo Robert A. Philhower photo Phillip J. Restle photo James D. (Jim) Warnock photo Xin Zhang photoChing Zhou photo Matthew M. Ziegler photo

Power Reduction in High-Performance Microprocessors - overview

Since the microprocessor industry first acknowledged power consumption as a primary design limitation, a number of power reduction techniques have been considered and successfully implemented in recent high-performance microprocessors. Techniques such as clock-gating, pulsed operation of latches, insertion of sleep transistors, use of high threshold CMOS devices on noncritical paths, and partitioning the chip into multiple clock and voltage domains have been extensively applied in microprocessors. When applied pervasively these techniques reduce the power consumption in most areas of the chip but the extent to which they are used may differ from unit to unit, and from processor to processor. In addition to these common approaches, there are power reduction techniques unique to a particular architecture, or implementation. The power reduction techniques employed by the POWER7(TM) microprocessor can be categorized into micro-architectural, logic and circuit levels, focusing on techniques that are either unique to POWER7(TM), or those that required significant changes to the design methodology, allowing an increase in scope. The power take-down work at every level tends to compete for resources with tuning of the micro-architecture to improve performance and timing take-down to increase the maximum frequency. In order to effectively use design resources available for power reduction, the team needs to precisely understand where power is spent and its sensitivity to various design options. A new power modeling methodology was deployed for POWER7(TM) that allowed the team to evaluate the impact of design changes and various power take-down actions before taking them to the designers. The power breakdown of the POWER7(TM) chiplet by type is shown in the figure below. The chiplet includes core, level 2 and 3 caches. The figure gives examples of the circuit-level power reduction techniques that were used in POWER7(TM). description