3D VLSI Integration - overview
In response to the increasing challenges in maintaining technology advancements through traditional scaling at a pace consistent with Moore's law, alternative methods to achieve enhanced system level performance are becoming increasingly important. 3D Technology has the potential to provide significant performance enhancements for several generations. Realization of this technology will require collaborative research and development across system architecture, design, and technology.
Significant changes to the basic circuit design, layout procedures and tools flow, as well as the routing of global signals and supplies (power/ground distribution, clock distribution, and I/O), will be required to accommodate the 3D technology features in stacked active chip designs. These changes can only be understood through a detailed evaluation of the impact of each of the unique 3D technology elements on the design. The Research Division is involved in leading the exploration of these new aspects of 3D VLSI chip design for future systems.
 Matt Wordeman, Joel Silberman, Gary Maier and Michael Scheuermann, "A 3D System Prototype of an eDRAM Cache Stacked over Processor-like Logic using Through Silicon Vias," to be presented at International Solid-State Circuit Conference (ISSCC), Feb. 2012.
 Yong Liu, Wing K. Luk, and Daniel J. Friedman, "A Compact Low-Power 3D I/O in 45nm CMOS," to be presented at International Solid-State Circuit Conference (ISSCC), Feb. 2012.
 M.G. Farooq, et. al, "3D Copper TSV Integration, Testing and Reliability," presented at International Electron Devices Meeting, Dec. 2011.