With technology scaling to minimum feature size on a wafer below 22nm, it's increasingly getting challenging to ensure the robustness and reliability of VLSI circuits. We are working on several projects ranging from technology modeling and simulation to on-chip characterization and in-field monitoring.
Recent Publications on Technology Robustness:
-- "Hardware-assisted 3D TCAD for Predictive Capacitance Extraction in 32nm SOI SRAMs" in Int. Electron Devices Meeting 2011.
Abstract: A comprehensive process/layout-independent TCAD flow is applied to FEOL/BEOL analysis/design of 32nm SOI SRAMs using, for the first time, iterative 3D TCAD capacitance extraction assisted by hardware data. Using the flow, FEOL junction capacitance is identified as the dominant factor affecting total bitline capacitance variation.
-- "Electrical Monitoring of Gate and Active Area Mask Misalignment Error" in VLSI Circuit Symposium 2011.
Abstract: A model-free, gate-diffusion (PC-RX) misalignment monitor circuit is implemented in 32nm CMOS for fabrication tool and layout ground rule characterization. It requires only DC current measurements compared to existing optical methods that require special microscopy equipment. An on-chip circuit is also designed to convert misalignment to digital data to enable post-Si repair.
Recent Publications on Technology Reliability:
-- "PBTI/NBTI Monitoring Ring Oscillator Circuits with On-Chip Vt Characterization and High Frequency AC Stress Capability" in VLSI Circuit Symposium 2011.
Abstract: We propose a new ring oscillator (RO) structure to monitor NBTI and PBTI effects separately. In addition, the unique circuit topology makes it possible to directly correlate the RO frequency degradation to transistor threshold voltage (Vt) degradation without relying on compact modeling with device parameters extracted from transistor-level measurements. It also enables high-speed (> GHz) AC BTI stress experiment with accompanying on-chip AC stress circuitry. The validity of the circuit concept is confirmed by measurements from a test chip in a high-k/metal gate SOI CMOS technology.
-- "Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies" in Int. Reliability Physics Symposium 2011.
Abstract: Ring oscillator (RO) structures that separate NBTI and PBTI effects are implemented in a high-k metal gate technology. The measurement results clearly show significant RO frequency degradation from PBTI as well as NBTI. For comparison, RO structures with the same principle are also implemented in a SiO2/poly-gate technology, where PBTI is negligible. Experimental results show noticeable frequency degradation under NBTI-only stress mode but negligible degradation under PBTI-only mode, which illustrates the validity of the proposed principle and structures.
-- "Bias Temperature Instability Model for Digital Circuits – Predicting Instantaneous FET Response" in Int. Reliability Physics Symposium 2011.
Abstract: We propose a semi-empirically enhanced BTI model to predict the instantaneous shift in VT due to both NBTI (in PFETs) and PBTI (in NFETs). Our proposed model uses same technology parameters as in existing model, and applied for both NBTI and PBTI. At every step of model generation, we demonstrate the correlation between our model and measured hardware. Further, we discuss the necessary steps to integrate our model with existing digital circuit simulators.