Atomic Layer Etching       


Robert L. Bruce photo photoERIC A. JOSEPH photo Nathan Marchack photo Hiroyuki  (Hiro) Miyazoe photo photo Hongwen  (Wendy) Yan photo

Atomic Layer Etching - overview

Over the course of the past few years, the semiconductor industry has continued to invent and innovate profoundly to adhere to Moore’s Law[1] and Dennard scaling[2]. From the introduction of new materials to the transition to non-planar FinFET devices, each new generation of technology bears considerable challenges for device fabrication. Looking at the 10nm technology node and beyond, this issue is compounded by the fact that scaling places inadvertent demands on etch processes, requiring control in single nanometer scale dimensions. This ever continuing trend to shrink device sizes coupled with the advent of novel materials, multi-component materials or even nanoscale materials, is driving the need for the ultimate etch solution: etching with atomic layer precision.


Atomic layer etch processes have gathered much interest recently. The promise of atomic scale precision may open up new and exciting possibilities in device fabrication:

First Atomic layer etch approaches have been proposed since the 1990's (see ALEt page). Recent activites also show an increase of activity in this area. However also other means of obtaining atomic scale precision have been examined. While enhanced energy control and reaction chemistry control schemes may show promise to attain atomic scale precision, one of the most attractive approaches currently under investigation is via employing flux control.  In this technique, an inert plasma is maintained continuously throughout the process, below the energy threshold for etch. Alternating cycles of deposition and etching are applied to the plasma process, eliminating some of the tradeoff behaviors typically associated with conventional plasma processes.


[1] G.E. Moore, “Cramming More Components onto Integrated Circuits”, Proc. IEEE 86 (1) 82-85 (1998) reprinted from Electronics, 114-117 (1965)

[2] R.H. Dennard, F.H. Gaensslein et al., “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions”, Proc. IEEE 87 (4), 668-678 (1999) reprinted from IEEE J. Sol. St. Cir. 9 (5), 256-268 (1974)