Logic Technologies       

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Logic Technologies - overview


Logic technology is the basis of the modern electronic world. Within the Semiconductor Technology Research (STR) group in IBM Research, scientists and engineers are researching ways to fabricate chips for the next generation production nodes and new business needs.

 

Moore's Law

Moore's Law is a well known prediction about how the size of features underpinning logic devices will continue to scale to smaller and smaller sizes in a regular cycle. The frequency of cycles has slowed in the past few generations, as material development has become more intense and atomistic limits are being hit. As the laws of physics begin to pose more serious challenges to sending more current through smaller devices, new architectures, materials, processing, and patterning techniques need to be developed.

 

Research Focus: Advanced Architectures

The field effect transistor (FET) has been the work horse of modern processors since the 1960s. With scaling to ever smaller dimensions, came the need for process and architecture innovation. Planar FETs had reached the end of its lifespan with need for a dramatic change in device layout, giving way to 3-Dimensional finFET architectures that were first commercialized in 2012 for 22nm technologies.

IBM has been a demonstrated industry leader in defining the future of these logic technologies, creating the industry’s first 7nm finFET devices in July 2015 and paving the way toward 5nm technologies utilizing nanosheet architectures in June 2017.

FinFET

[C. Lavoie et al. ECS Trans 2017, D. Guo et al. VLSI 2016]
 

FinFETs are multigate transistor solutions that have been heavily used in recent technology nodes. In finFET structures, as opposed to planar devices, the channel is shaped into a tall, thin silicon fin to allow for great scalability of the device and improved performance.

Extreme process control and material innovation is required to form such fragile structures while maintaining device performance. IBM has demonstrated feasibility in utilizing new materials such as SiGe channel as a major technology element in 10nm nodes and beyond. Additional technology elements, like EUV lithography, have been persued for 7nm finFET technologies and have been shown to give improved performance from its 10nm predecesor.

 

Nanosheet

Nanosheet transistors provides similarly outstanding short channel control compared to finFETs, with the important distinction that the gate of the device surrounds the channel material. Nanosheet transistor provides much improved design flexibility with the feasibility of adjustable nanosheet width, compared to FINFET.

IBM researchers have demonstrated the unique structure and its advantages at 2017 VLSI. These nanosheet architectures are shown to provide performance and scalability suitable for 5nm technologies and beyond.

  nanosheet  N. Loubet, et al VLSI 2017

 

 

Patterning & EUV

Our exceptional patterning team comprises researchers in lithography, etch, and computational lithography, all working to develop leading-edge techniques for creating the extremely small features required for the next generation of logic devices, such as those for the 7nm node and beyond. A key process technology element for pushing these limits is Extreme Ultraviolet (EUV) lithography. In a single exposure, EUV can create a high-resolution pattern that is unattainable by prior semiconductor patterning processes. Enabling EUV patterning requires specialized equipment, processes, and know-how, all found at IBM’s research labs in Albany, NY and Yorktown Heights, NY.

 

In addition to exploring the fundamental limits of EUV lithography, IBM is also focused on pushing the limits of fine patterning. By understanding the interactions between film stacks, patterning materials, and etch technologies, very high resolution and high-fidelty structures have been created to enable new device architecture exploration. On a daily basis, feature sizes less than 10nm, on pitches less than 30nm, are demonstrated in IBM Research, whether via directly-printed EUV, patterning multiplication, or directed self-assembly.

While developing, and routinely utilizing, the advanced patterning processes created at IBM, extremely-large and high-frequency data sets are generated than can be utilized to leverage the advanced cognitive manufacturing knowhow that has been developed in IBM Research. To this end, IBM is actively engaged with the semiconductor equipment vendor community to demonstrate this capability in increasing reliability and insight on their toolsets. Additionally, cognitive manufacturing is being used to gain insight into semiconductor patterning & process control, in order to deliver increasingly-complex patterned structures.

 

Materials Research

To improve both electrical performance and processing, the IBM team is investigating new materials that will result in better yielding devices. Optimization of currently used materials is always important, as well.

airgap1  

In the middle of line, air has been a relatively new material incorporated into device structures to reduce capacitance. These air spacers prevent electrical charge from accumulating between metal contacts and reduce the power required to switch the transistor.

  airgap2

In the back end, the metals used for interconnects are constantly under evaluation and optimization. The industry standard is to use copper as a primary conductor, but other metals, paired with the right processing and barriers, could be contenders to replace copper as critical dimensions shrink further. Recently, some work using cobalt as the interconnect metal has been published. To extend the life of copper in manufacturing devices, alternative barrier schemes such as cobalt or ruthenium are being discussed and studied, as well.

  ru

 

 

Device Characterization and Failure Analysis

To quality and quantify all these novel materials and device architectures, our Albany site is continually equipped with new & powerful electrical test, metrology, and inspection tools. For more information, see our Fab & Characterization Capabilities page.