Fab and Characterization Capabilies       

links

 photo photo Adra V (Tory) Carr photo photoJeff Shearer photoJames H. (Jim) Stathis photo Charles J. Taft photo photo

Fab and Characterization Capabilies - overview


Reaching Forward from Manufacturing Roots:

Albany leverages decades of manufacturing expertise to balance the needs of agile development with conscientious FAB process controls. This includes continuous collection and archiving of operational data outputs using a Manufacturing Production Control System. This use of manufacturing sourced infrastructure provides first tier experimental controls and data collection. Once captured, data can be reviewed using multiple IBM developed web-tools or exported for deep analysis and/or machine learning (see our blog post here). Whether inline or offline, the ability to efficiently assess experiments is key to a development and research mission.

IBM Albany has strategic partnerships with leading semiconductor foundries, including GlobalFoundries and Samsung, to collaborate and further develop a sustainable process flow at next generation nodes. A large number of equipment suppliers are also onsite including Applied Materials, ASML, LAM and Tokyo Electron providing onsite support and engaging in joint development projects.

 

Facility overview

SUNY Poly's Albany NanoTech Complex (ANT), home to IBM's semiconductor research and development, is a fully integrated 300mm research facility dedicated to CMOS technology reseach, innovation and process flexibility for future technology node research. Significant investment by New York State and the University of Albany has helped to create a one-of-a-kind research collaboration facility in Albany, NY and allowing for new materials and process introduction to chip manufacturing.

   

 

SUNY Poly's ANT facility has four different cleanrooms dedicated to 300mm wafer production.  NanoFab South and NanoFab South Annex were completed in 2003 and 2004 respectively and include a combined 32K square feet of cleanroom space.  NanoFab North was completed in 2005 and houses 35K square feet of Class 1 cleanroom space.  Immediately adjacent is NanoFab Central which, completed in 2009, added an additional 15K square feet of Class 1 cleanroom space.  The latest addition of NanoFab Xtension (completed in 2013) includes an additional 45K square feet of cleanroom space.

The combined 130K square feet of cleanroom R&D space contain over 100 wafer processing and inline metrology tools for 300mm wafer processing. These advanced wafer processing platforms are used for development in the areas of thin film deposition, metalization, advanced lithography, planarization, etch, wet cleaning and ion implantation.  The flexibility for unit process development, novel materials and partner collaboration makes ANT a unique semiconductor research facility. 

 

Device and material characterization capabilities in Albany:

Automated Inline Metrology Capability:

CD-SEM measurement 

CD Scanning Electron Microscopes for automated Top-down Critical Feature imaging and Dimension measurement

Ellipsometry

Film property measurement capabilities for both blanket and integrated wafer applications

Scatterometry

In-structure measurement capability for device equivalent arrays supplement process insight

XRD/XPS     

Non-destructive elemental and structural X-Ray based measurements

Brightfield PLY

Full build/integrated wafer monitoring using Brightfield PLY including SEM imaging and Classificaiton

FM/Metallics  

Equipment monitoring for Particle adders as small as 40nm as well as TXRF and VPDA Metallic contamination monitoring is routine

 

Offline Material and Structural Characterisation Capabilities
A fully independent PFA lab with STEM/SEM capabilities supports all IBM development activites on site. This analytical lab facility addresses the need to continue to provide the analytical characterizations to support IBM’s semiconductor research and development activities at Albany Nanotech. It provides many options for tool owners, process engineers and integrators to analyze and investigate their materials and process related issues.

Since 2007, our lab keeps providing material and structural characterization on all of IBM’s emerging technologies on 22, 14 and 10 nm and 7nm nodes, including both FEOL and BEOL structures, such as conventional CMOS device, advanced SOI devices (ETSOI, UTBB), high-k metal gate (HKMG) stacks, bulk/ SOI FinFET device, SiGe FinFET device, Nanosheet FinFET device, Vertical transport FET device, advanced memory device, advanced metallization and interconnects.

 

 

(a) High resolustion STEM image of nanosheet structure, (b) and (c) in plane and out of plane lattice strain maps obtained by GPA [J. Li, et al. 2016 Microscopy & Microanalysis]

 

EDX map showing Mn segregation outside of a Co barrier in Copper interconnects [N. Takeshi, et al IEDM 2015]
 

Instruments & techniques include Mechanical Polishing, Ultra-low Energy and Concentrate Ion Milling; DualBeam Focused Ion Beam/Scanning Electron Microscopy; Scanning Electron Microscopy; Transmission Electron Microscopy; Scanning Transmission Electron Microscopy; and Aberration Corrected Electron Microscopy.

Specifically, the lab can provide:

  • Cross-sectional SEM analysis
  • High resolution bright/dark field TEM imaging
  • Energy-dispersive X-ray spectroscopy (EDX)/Electron Energy Loss Spectroscopy (EELS) elemental analysis
  • EDX/EELS spectrum imaging
  • Nanobeam electron diffraction strain measurement
  • Precession electron diffraction strain measurement
  • Phase and Orientation mapping

Electrical Testing and Reliability Capability:
For wafer level testing, multiple Fully Automatic Parametric testers are located in the Central Fab. They include integrated automated control and data collection systems to allow for multiple test points along a wafer build, including transistor level test data, ramped voltage stress for reliability screens, and wiring level parametric data and yield data. An electrical test result database archives collected data, enables calculated parameters, provides specification yield results and tabulates results at the Wafer, Chip, and Macro Levels, all linked to the corresponding process and metrology data.

Offline, or "bench" testing capability provides additional specialized wafer level and package level testing for deeper investigation over a temperature range from -55C to +400C, such as:

  • Capacitance and Conductance measurements
  • Charge pumping measurement 
  • Mobility measurement
  • High-speed pulsed IV testing
  • Constant-voltage stress, AC stress, and ramp stress for
    • TDDB (Time-dependent dielectric breakdown)
    • BTI (Bias-temperature instability)
    • HC (hot carrier) degradation
  • Triangular voltage sweep test
  • Memory testing

Dicing and Bonding systems support integrated/3D element testing. Additional testing capability is always being deployed to support new device and package structures as needed.