Design Automation (Computer Systems Design sub-discipline)       

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Design Automation (Computer Systems Design sub-discipline) Publications



2014

Dynamically tune power proxy architectures
Emrah Acar, Pradip Bose, Bishop C Brock, Alper Buyuktosunoglu, Michael S Floyd, Maria L Pesantez, Gregory S Still
US Patent 8,635,483


A Simulation Study of Oxygen Vacancy-Induced Variability in HfO₂/Metal Gated SOI FinFET
Amit Ranjan Trivedi, Takashi Ando, Amith Singhee, Pranita Kerber, Emrah Acar, David J Frank, Saibal Mukhopadhyay
2014 - ieeexplore.ieee.org, IEEE

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
James Warnock, Yuen Chan, Hubert Harrer, Sean Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey Zitz, Adam Jatkowski, Gerald Strevig, others
2014 - ieeexplore.ieee.org, IEEE

Integrated design environment for nanophotonics
Emrah Acar, Michael P Beakes, William M Green, Jonathan E Proesel, Alexander V Rylyakov, Yurii A Vlasov
US Patent 8,627,240

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis
Mahmoud Elbayoumi, Mihir Choudhury, Victor Kravets, Andrew Sullivan, Michael Hsiao, Mustafa Elnainay
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, pp. 1--6, 2014


2013

Low Cost Concurrent Error Masking Using Approximate Logic Circuits
Mihir R Choudhury, Kartik Mohanram
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 32(8), 1163--1176, IEEE, 2013

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Subhendu Roy, Mihir Choudhury, Ruchir Puri, David Z Pan
Proceedings of the 50th Annual Design Automation Conference, pp. 48, 2013

Design Routability Using Multiplexer Structures
Charles J Alpert, Victor N Kravets, Zhuo Li, Louise H Trevillyan, Ying Zhou
US Patent 20,130,086,537

5.5 GHz system z microprocessor and multi-chip module
J Warnock, Yuen H Chan, Hubert Harrer, D Rude, Ruchir Puri, S Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, M Mayo, others
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, pp. 46--47

Hardware-corroborated Variability-Aware SRAM Methodology
R Joshi, Rouwaida Kanj, S Butt, Emrah Acar, D Lea, D Sciacca
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on, pp. 344--349

Differential FET structures for electrical monitoring of overlay
Emrah Acar, Aditya Bansal, Amith Singhee
US Patent 8,409,882

Performance driven layout optimization using morphing of a basis set of representative layouts
Emrah Acar, Aditya Bansal, Rama N Singh, Amith Singhee
US Patent 8,510,699

Best clock frequency search for FPGA-based design
Sunil Shukla, Perry Cheng, Rodric Rabbah
US Patent 8,566,768


2012

Spatial variation decomposition via sparse regression
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane Boning, Emrah Acar, T Liu, Rob A Rutenbar
IC Design \& Technology (ICICDT), 2012 IEEE International Conference on, pp. 1--4

An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring
Huapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun, Haifeng Qian, Shi-Chune Yao
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, pp. 642--647

Subtractive Router for Tree-Driven-Grid Clocks
Haifeng Qian, Phillip J Restle, Joseph N Kozhaya, Clifford L Gunion
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 31(6), 868--877, IEEE, 2012

Examination of Process Parameter Variations
Emrah Acar, Hendrik Mau, Andy Heinig, Bing Li, Ulf Schlichtmann
Process Variations and Probabilistic Integrated Circuit Design, pp. 69--89, Springer, 2012

Methods of Parameter Variations
Christoph Knoth, Ulf Schlichtmann, Bing Li, Min Zhang, Markus Olbrich, Emrah Acar, Uwe Eichler, Joachim Haase, Andr\'e Lange, Michael Pronath
Process Variations and Probabilistic Integrated Circuit Design, pp. 91--179, Springer, 2012

Regular local clock buffer placement and latch clustering by iterative optimization
Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock
US Patent 8,104,014

DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM
Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N Singh, Aditya Bansal
Quality Electronic Design (ISQED), 2012 13th International Symposium on, pp. 470--476

Circuit technique to electrically characterize block mask shifts
Emrah Acar, Aditya Bansal, Dureseti Chidambarrao, Liang-Teck Pang, Amith Singhee
US Patent App. 13/488,532

Power Management of Multi-Core Chips: Challenges and Pitfalls
Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta S. Gupta, Michael B. Healy, Hans Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger
Design, Automation & Test in Europe Conference & Exhibition, pp. 977--982, 2012


2011

Floorplanning challenges in early chip planning
Jeonghee Shin, John A Darringer, Guojie Luo, Merav Aharoni, Alexey Y Lvov, G Nam, Michael B Healy
SOC Conference (SOCC), 2011 IEEE International, pp. 388--393

Design, CAD and technology challenges for future processors: 3D perspectives
J. Burns, G. Carpenter, E. Kursun, R. Puri, J. Warnock, M. Scheuermann
2011 ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 212

Electrical monitoring of gate and active area mask misalignment error
A Bansal, A Singhee, E Acar, G Costrini
VLSI Circuits (VLSIC), 2011 Symposium on, pp. 220--221

Abstraction and microarchitecture scaling in early-stage power modeling
Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard Eickemeyer
High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, pp. 394--405

Error Tolerance in Server Class Processors
J A Rivers, M S Gupta, J Shin, P N Kudva, P Bose
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 30(7), 945--959, IEEE, 2011

Floorplanning Challenges in Early Chip Planning
Jeonghee Shin, John Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam and Michael Healy
International SOC Conference, 2011

Early chip planning cockpit
Jeonghee Shin, J A Darringer, Guojie Luo, A J Weger, C L Johnson
Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1 -4


2010

INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA
E Acar, K B Agarwal, D Jamsek, S R Nassif
US Patent App. 20,100/262,412

Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer Correlation
W. Zhang, X. Li, E. Acar, Y. Liu, R. Rutenbar
International Conference on Computer Aided Design,, 2010

BLENDED MODEL INTERPOLATION
E Acar, D Jamsek, S R Nassif
US Patent App. 20,100/262,409

COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION
E Acar, K B Agarwal, D Jamsek, S R Nassif
US Patent App. 20,100/262,413


Power-efficient, Reliable Microprocessor Architectures: Modeling and Design Methods
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger and Victor V. Zyuban
In Proceedings of IEEE International Symposium, GLSVLSI, pp. 299 - 304, pp. 299--304, IEEE, ACM, 2010
Abstract

Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Z Li, D A Papa, C J Alpert, S Hu, W Shi, C Sze, Y Zhou
Proceedings of the 19th international symposium on Physical design, pp. 75--82, ACM, 2010

Detecting tangled logic structures in VLSI netlists
T Jindal, C J Alpert, J Hu, Z Li, G J Nam, C B Winn
Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 603--608

ITOP: Integrating timing optimization within placement
N Viswanathan, G J Nam, J A Roy, Z Li, C J Alpert, S Ramji, C Chu
Proceedings of the 19th international symposium on Physical design, pp. 83--90, 2010

What makes a design difficult to route
C J Alpert, Z Li, M Moffitt, G Nam, J Roy, G Tellez
Proceedings of the 19th international symposium on Physical design, pp. 7--12, 2010


2009

64-bit prefix adders: Power-efficient topologies and design solutions
C Zhou, B M Fleischer, M Gschwind, R Puri
Custom Integrated Circuits Conference, pp. 179--182, 2009

Yield Estimation of SRAM Circuits using  Virtual SRAM Fab
A. Bansal, A. Singhee, E. Acar, F. Luen, etal
International Conference on Computer Aided Design, 2009

Charge-based circuit analysis
Emrah Acar, Bhavna Agrawal, Peter Feldmann, Ying Liu, Steven G Walker
US Patent 7,519,526

Exploring High-Level Languages for Accelerator Design
Minsik Cho, Geert Janssen, Indira Nair and Jeonghee Shin
Workshop on Hardware Accelerators for High-Performance Computing, 2009

Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations
R Kanj, Z Li, R V Joshi, F Liu, S R Nassif
Semiconductor Manufacturing, IEEE Transactions on 22(1), 22--30, IEEE, 2009

Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions
KI JIN HAN, M. Swaminathan
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2009

Improving Testability and Soft-Error Resilience through Retiming
SMITA KRISHNASWAMY, IL Markov, JP Hayes
DAC 2009 - Design Automation Conference

A Fully Polynomial Time Approximation Scheme for Timing Constrained Minimum Cost Layer Assignment
Shiyan Hu, ZHUO LI, Charles Alpert
TCASII 2009 - IEEE Transactions on Circuits and Systems II: Express Briefs

Signature-based SER analysis and Design of Logic circuits
SMITA KRISHNASWAMY, SM Plaza, IL Markov, JP …
IEEE Trans. on CAD, 2009

A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
S Hu, Z Li, C J Alpert
Design Automation Conference, 2009, pp. 580--584, IEEE

A faster approximation scheme for timing driven minimum cost layer assignment
S Hu, Z Li, C J Alpert
Proceedings of the 2009 international symposium on Physical design, pp. 167--174

DeltaSyn: An Efficient Logic Difference Optimizer for ECO Synthesis
Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, Ruchir Puri
International Conference on Computer Aided Design, pp. 789--796, 2009


2008



IBM Research, 3D IC Workshop
E Acar
National Tsing Hua University, Hsinchu, Taiwan, 2008

A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache SRAM lifetime
Jeonghee Shin, Victor Zyuban, Pradip Bose, Timothy M Pinkston
ACM SIGARCH Computer Architecture News, pp. 353--362, 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes
R Kanj, R Joshi, Z Li, JB Kuang, H Ngo, Y Zhou, W Shi, S Nassif
Proceeding of the 13th international symposium on Low power electronics and design, pp. 87--92, 2008

A Root-Finding Method for Assessing SRAM Stability
R Kanj, Z Li, R Joshi, F Liu, S Nassif
Quality Electronic Design, 2008, pp. 804--809


Path smoothing via discrete optimization
M D Moffitt, D A Papa, Z Li, C J Alpert
Design Automation Conference, 2008, pp. 724--727

Pyramids: An efficient computational geometry-based approach for timing-driven placement
T Luo, D A Papa, Z Li, CN Sze, C J Alpert, D Z Pan
Computer-Aided Design, 2008, pp. 204--211

On the role of timing masking in reliable logic circuit design
S Krishnaswamy, IL Markov, JP Hayes
Design Automation Conference, 2008. DAC 2008. …, 2008 - ieeexplore.ieee.org

A polynomial time approximation scheme for timing constrained minimum cost layer assignment
S Hu, Z Li, C J Alpert
Computer-Aided Design, 2008, pp. 112--115

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
S Krishnaswamy, GF Viamontes, IL Markov, …
2008 - portal.acm.org

RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm
D A Papa, T Luo, M D Moffitt, CN Sze, Z Li, G J Nam, C J Alpert, I L Markov
Proceedings of the 2008 international symposium on Physical design, pp. 2156--2168, IEEE

Fast interconnect synthesis with layer assignment
Z Li, C J Alpert, S Hu, T Muhmud, S T Quay, P G Villarrubia
Proceedings of the 2008 international symposium on Physical design, pp. 71--77

Exploring power management in multi-core systems
Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer
Proceedings of the 13th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 708--713

Handbook of Algorithms for Physical Design Automation
C J Alpert, D P Mehta, S S Sapatnekar
2008 - books.google.com, Auerbach Publications

RUMBLE: An Incremental, Timing Driven, Physical-Synthesis Optimization Algorithm
DAVID A PAPA, Tao Luo, MICHAEL D MOFFITT, Chin Ngai Sze (CLIFF), ZHUO LI, Gi
Joon Nam, Charles Alpert, Igor Markov - TCAD 2008 - IEEE Transactions on Computer-Aided Design

Keeping hot chips cool: are IC thermal problems hot air?
R Puri, D Varma, D Edwards, A J Weger, P Franzon, A Yang, S Kosonocky
Proceedings of the 45th annual Design Automation Conference, pp. 634--635, 2008


2007

Timing-Aware Power Minimization via Extended Timing Graph Methods
H. Qian, E. Acar
Journal of Low Power Electronics 3(3), 318--326, American Scientific Publishers, 2007

Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
P Li, Z Feng, E Acar
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15(11), 1205--1214, IEEE, 2007

A Temperature-Aware Power Estimation Methodology
M S Govindan, S W Keckler, S Nassif, E Acar
2007 - cs.utexas.edu, Computer Science Dept., Univ. of Texas at Austin

A framework for architecture-level lifetime reliability modeling
Jeonghee Shin, Victor Zyuban, Zhigang Hu, Jude A Rivers, Pradip Bose
Dependable Systems and Networks, 2007. DSN'07. 37th Annual IEEE/IFIP International Conference on, pp. 534--543

Probabilistic congestion prediction with partial blockages
C J Alpert, Z Li, S T Quay
US Patent 7,299,442

Probabilistic congestion prediction with partial blockages
Z Li, C J Alpert, S T Quay, S Sapatnekar, W Shi
Proc, pp. 841--846, 2007


Method and Apparatus for Congestion Based Physical Synthesis
C J Alpert, A K Karandikar, Z Li, C N Sze
US Patent App. 11/748,514


A More Effective Ceff for Slew Estimation
Y Zhou, Z Li, RN Kanj, DA Papa, S Nassif, W Shi
Integrated Circuit Design and Technology, 2007, pp. 1--4

Fast algorithms for slew constrained minimum cost buffering
Shiyan Hu, Charles Alpert, Shrirang Karandikar, ZHUO LI, Weiping Shi, Chin Ngai Sze (CLIFF)
TCAD 2007 - IEEE Transactions on Computer-Aided Design

Physical synthesis comes of age
CJ Alpert, C Chu, PG Villarrubia
Proc. Int. Conf. on Computer Aided Design, 2007 - eng.iastate.edu

Fast electrical correction using resizing and buffering
SK Karandikar, CJ Alpert, MC Yildiz, P Villarrubia, S Quay, T Mahmud
Design Automation Conference, 2007, pp. 553--558

Wire sizing for non-tree topology
Z Li, Y Zhou, W Shi
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 26(5), 872--880, IEEE, 2007

The nuts and bolts of physical synthesis
C J Alpert, S Karandikar, Z Li, G J Nam, S Quay, H Ren, C Sze, P G Villarrubia, M Yildiz
Proceedings of the 2007 international workshop on System level interconnect prediction, pp. 89--94

The coming of age of physical synthesis
CJ Alpert, C Chu, PG Villarrubia
Proceedings of the 2007 IEEE/ACM international conference on …, 2007 - portal.acm.org

Tracking Uncertainty with Probabilistic Logic Circuit Testing
S Krishnaswamy, IL Markov, JP Hayes
IEEE Design & Test of Computers, 2007 - ieeexplore.ieee.org

Multi-core design automation challenges
JA Darringer
Design Automation Conference, pp. 760 : 764, 2007

RQL: Global placement via relaxed quadratic spreading and linearization
N Viswanathan, G J Nam, C J Alpert, P Villarrubia, H Ren, C Chu
44th ACM/IEEE Design Automation Conference, 2007, pp. 453--458

Hippocrates: First-do-no-harm detailed placement
H. Ren, D.Z. Pan, C.J. Alpert, G.J. Nam, P. Villarrubia
Proceedings of the 2007 Asia and South Pacific Design Automation Conference, pp. 141--146

A new methodology for interconnect parasitics extraction considering photo-lithography effects
Y Zhou, Z Li, Y Tian, W Shi, F Liu
Design Automation Conference, 2007, pp. 450--455

Performance modeling for early analysis of multi-core systems
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp. 209--214, 2007

Enhancing design robustness with reliability-aware resynthesis and logic simulation
S Krishnaswamy, SM Plaza, IL Markov, JP …
Proceedings of the 2007 IEEE/ACM international …, 2007 - portal.acm.org

Scalable sequential equivalence checking across arbitrary design transformations
H Mony, V Paruthi, R Kanzelman, G Janssen
Computer Design, 2006. ICCD 2006. International Conference …, 2007 - ieeexplore.ieee.org

Techniques for fast physical synthesis
C J Alpert, S K Karandikar, Z Li, G J Nam, S T Quay, H Ren, CN Sze, P G Villarrubia, M C Yildiz
Proceedings of the IEEE 95(3), 573--599, IEEE, 2007

Path-Based Buffer Insertion
CN Sze, CJ Alpert, J Hu, W Shi
IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED …, 2007 - ieeexplore.ieee.org


2006

Power grid analysis using a flexible conjugate gradient algorithm with sparsification
Peter Feldmann, Roland W Freund, Emrah Acar
Technical Report, Citeseer, 2006

Characterization of total chip leakage using inverse (reciprocal) gamma distribution
E Acar, K Agarwal, S R Nassif
Circuits and Systems, 2006, pp. 4--pp

Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA)
Emrah Acar, Peter Feldmann
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp. 4--pp

Advances in performance modeling for interconnect and memory
E Acar, P Li
International Conference on Computer Aided Design: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design: San Jose, California

Methods for estimating decoupling capacitance of nonswitching circuit blocks
S R Nassif, K Agarwal, E Acar
Circuits and Systems, 2006, pp. 4--pp

When are Multiple Gate Errors Significant in Logic Circuits?
S Krishnaswamy, IL Markov, JP Hayes
SELSE Workshop, 2006 - eecs.umich.edu

A new RLC buffer insertion algorithm
Z Jiang, S Hu, J Hu, Z Li, W Shi
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 557

Timing-driven Steiner trees are (practically) free
CJ Alpert, AB Kahng, CN Sze, Q Wang
Proceedings of the 43rd annual conference on Design …, 2006 - portal.acm.org

From single core to multi-core: preparing for a new exponential
J Parkhurst, J Darringer, B Grundmann
ICCAD, pp. 67-72, 2006

Buffer insertion in large circuits with constructive solution search techniques
M Waghmode, Z Li, W Shi
Proceedings of the 43rd annual Design Automation Conference, pp. 301, 2006


An O (bn2) time algorithm for optimal buffer insertion with b buffer types
Z Li, W Shi
Design, Automation and Test in Europe, 2005, pp. 484--489, IEEE, 2006

Accurate estimation of global buffer delay within a floorplan
CJ Alpert, J Hu, SS Sapatnekar, CN Sze
Computer-Aided Design of Integrated Circuits and Systems, …, 2006 - ieeexplore.ieee.org

Fast algorithms for slew constrained minimum cost buffering
S Hu, C J Alpert, J Hu, S Karandikar, Z Li, W Shi, CN Sze
Proceedings of the 43rd annual Design Automation Conference, pp. 313, 2006

A fast hierarchical quadratic placement algorithm
G J Nam, S Reda, C J Alpert, P G Villarrubia, A B Kahng
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 25(4), 678--691, IEEE, 2006


2005

Method for determining the leakage power for an integrated circuit
E Acar, A Devgan, Y Liu, S R Nassif, H Su, others
US Patent 6,842,714

A waveform independent gate model for accurate timing analysis
P Li, E Acar
Computer Design: VLSI in Computers and Processors, 2005, pp. 363--365

A more effective Ceff
S R Nassif, Z Li
Quality of Electronic Design, 2005, pp. 648--653

Fast interconnect optimization
Z Li
Ph.D. Thesis, 2005

A mask reuse methodology for reducing system-on-a-chip cost
S Bhattacharya, J Darringer, D Ostapko, Y Shin, &
ISQED - Best Paper, 2005

An efficient surface-based low-power buffer insertion algorithm
RR Rao, D Blaauw, D Sylvester, CJ Alpert, S Nassif
International Symposium on Physical Design: Proceedings of …, 2005 - eecs.umich.edu

Logic circuit testing for transient faults
S Krishnaswamy, IL Markov, JP Hayes
Test Symposium, 2005. European, 2005 - ieeexplore.ieee.org

Practical techniques to reduce skew and its variations in buffered clock networks
P Li, S Khatri, A Rajaram, P McGuinness, C Alpert
Proceedings of the 2005 IEEE/ACM International conference on …, 2005 - portal.acm.org

Placement stability metrics
C J Alpert, G J Nam, P Villarribua, M C Yildiz
Design Automation Conference, 2005, pp. 1144--1147

Computational geometry based placement migration
T Luo, H Ren, CJ Alpert, DZ Pan
Proceedings of the 2005 IEEE/ACM International conference on …, 2005 - portal.acm.org

An O (bn\^{} 2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
Z Li, W Shi
Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, pp. 1329, 2005

A semi-persistent clustering technique for VLSI circuit placement
C Alpert, A Kahng, G J Nam, S Reda, P Villarrubia
Proceedings of the 2005 international symposium on Physical design, pp. 200--207

Making fast buffer insertion even faster via approximation techniques
Z Li, CN Sze, C J Alpert, J Hu, W Shi
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pp. 13--18

A fast algorithm for optimal buffer insertion
W Shi, Z Li
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 24(6), 879--891, IEEE, 2005

An efficient and effective detailed placement algorithm
M Pan, N Viswanathan, C Chu
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM …, 2005 - ieeexplore.ieee.org

Diffusion-based placement migration
H Ren, DZ Pan, CJ Alpert, P Villarrubia
Proceedings of the 42nd annual conference on Design …, 2005 - portal.acm.org

Longest-path selection for delay test under process variation
X Lu, Z Li, W Qiu, DMH Walker, W Shi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(12), 1924--1929, Institute of Electrical and Electronics Engineers, Inc, 445 Hoes Ln, Piscataway, NJ, 08854-1331, USA,, 2005

The ISPD2005 placement contest and benchmark suite
G J Nam, C J Alpert, P Villarrubia, B Winter, M Yildiz
Proceedings of the 2005 international symposium on Physical design, pp. 220

Accurate reliability evaluation and enhancement via probabilistic transfer matrices
S Krishnaswamy, GF Viamontes, IL Markov, …
Design, Automation and Test in Europe, 2005. …, 2005 - ieeexplore.ieee.org


2004

Advanced waveform models for the nano-meter regime
S R Nassif, E Acar
ACM/IEEE International Workshop on Timing Issues, 2004

K longest paths per gate (KLPG) test generation for scan-based sequential circuits
W Qiu, J Wang, DMH Walker, D Reddy, X Lu, Z Li, W Shi, H Balachandran
Test Conference, 2004, pp. 223--231

Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance
P Stanley-Marbell, D Marculescu
Proceedings of the conference on Design, Automation and Test in Europe, DATE '04, 2004

Longest Path Selection for Delay Test Under Process Variation
Xiang Lu, ZHUO LI, Wangqi qiu, Weiping Shi, D. M. H. Walker
ASPDAC 2004 - Proceedings of 9th Asian and South Pacific Design Automation Conference

Were the good old days all that good? EDA then and now
WH Joyner, S Rawat, J Darringer, D Gajski, PO …
Design Automation Conference, 2004. Proceedings. 41st, 2004 - ieeexplore.ieee.org

A place and route aware buffered Steiner tree construction
CN Sze, J Hu, CJ Alpert
with EDA Technofair Design Automation Conference Asia and …, 2004 - doi.ieeecomputersociety.org

At-speed test for path delay faults using practical techniques
W Qiu, J Wang, X Lu, Z Li, DMH Walker, W Shi
Current and Defect Based Testing, 2004, pp. 61--66

A circuit level fault model for resistive shorts of MOS gate oxide
X Lu, Z Li, W Qiu, H Walker, W Shi
5th international workshop on microprocessor test and verification, 2004

Parade: parametric delay evaluation under process variation [ic modeling]
X Lu, Z Li, W Qiu, DMH Walker, W Shi
Quality Electronic Design, 2004, pp. 276--280

Fast and Flexible Buffer Trees that Navigate the Physical Layout Environment
CJ Alpert, M Hrkic, J Hu, ST Quay
IEEE/ACM Design Automation Conference, 2004

Tutorial on verification of distributed cache memory protocols
S German, G Janssen
Formal Methods in Computer Aided Design, 2004 - cs.utah.edu

A statistical fault coverage metric for realistic path delay faults
W Qiu, X Lu, J Wang, ZHUO LI, DMH Walker, W Shi
VTS 2004 - 22nd IEEE VLSI Test Symposium.

A fast algorithm for identifying good buffer insertion candidate locations
CJ Alpert, M Hrkic, ST Quay
Proceedings of the 2004 international symposium on Physical …, 2004 - portal.acm.org

Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique
C Alpert, C Chu, G Gandham, M Hrkic, J Hu, C …
IEEE Transactions on Computer-Aided Design of Integrated …, 2004 - ieeexplore.ieee.org

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
C V Kashyap, C J Alpert, F Liu, A Devgan, F Inc, CA Sunnyvale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(4), 509--516, 2004

Closed-form delay and slew metrics made easy
C J Alpert, F Y Liu, C V Kashyap, A Devgan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(12), 1661, 2004

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
W Shi, Z Li, C J Alpert
Proceedings of the 2004 Asia and South Pacific Design Automation Conference, pp. 609--614


2003

Leakage and leakage sensitivity computation for combinational circuits
Emrah Acar, Anirudh Devgan, Rahul Rao, Ying Liu, Haihua Su, Sani Nassif, Jeffrey Burns
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 96--99

Predicting short circuit power from timing models
Emrah Acar, Ravishankar Arunachalam, Sani R Nassif
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, pp. 277--282

Optimal shielding/spacing metrics for low power design
Ravishankar Arunachalam, Emrah Acar, Sani R Nassif
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on, pp. 167--172

Power grid reduction based on algebraic multigrid principles
Haihua Su, Emrah Acar, Sani R Nassif
Proceedings of the 40th annual Design Automation Conference, pp. 109--112, 2003

Full chip leakage estimation considering power supply and temperature variations
Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani Nassif
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 78--83


LOGIC SYNTHESIS OVERVIEW - Book Chapter
RK Brayton, JA Darringer
The Best of ICCAD, 2003

First CADathlon programming contest held at 2002 ICCAD
S Hassoun, G Janssen
IEEE Design & Test of Computers, 2003 - cs.uic.edu

Design Systems Evolution and the Need for a Standard Data Model
J Darringer, J Morrell, IBM Microelectronics
Electronic Design Processes 2003 Workshop, 2003 - eda.org

Process variation dimension reduction based on svd
Z Li, X Lu, W Shi
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2003

A consumer report on BDD packages
G Janssen, IBMTJWR Center, NY Yorktown Heights
Integrated Circuits and Systems Design, 2003. SBCCI 2003. …, 2003 - ieeexplore.ieee.org

CodSim-a combined delay fault simulator
W Qiu, X Lu, Z Li, MH Walker, W Shi
Defect and Fault Tolerance in VLSI Systems, 2003, pp. 79--86

Minimum buffered routing with bounded capacitive load for slew rate and reliability control
C J Alpert, A B Kahng, B Liu, I I Mandoiu, A Z Zelikovsky
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(3), 241, 2003

Closed form expressions for extending step delay and slew metrics to ramp inputs
CV Kashyap, CJ Alpert, F Liu, A Devgan
Proceedings of the 2003 international symposium on Physical …, 2003 - portal.acm.org

SEAS: a system for early analysis of SoCs
S Bhattacharya, WE Dougherty, I Nair, J Darringer …
Proceedings of the 1st IEEE/ACM/IFIP international …, 2003 - portal.acm.org

Effective free space management for cut-based placement via analytical constraint generation
C Alpert, G J Nam, P Villarrubia
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 22(10), 1343--1353, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2003

A circuit level fault model for resistive bridges
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D M H Walker
ACM Trans. Des. Autom. Electron. Syst. 8(4), 546--559, ACM, 2003
Abstract

Optimal Path Routing in Single-and Multiple-Clock Domain Systems
S Hassoun, CJ Alpert
IEEE Transactions on Computer-Aided Design of Integrated …, 2003 - doi.ieeecomputersociety.org

Buffer insertion with adaptive blockage avoidance
J Hu, CJ Alpert, ST Quay, G Gandham
Computer-Aided Design of Integrated Circuits and Systems, …, 2003 - ieeexplore.ieee.org

Delay and slew metrics using the lognormal distribution
CJ Alpert, F Liu, C Kashyap, A Devgan
Proceedings of the 40th conference on Design automation, 2003 - portal.acm.org

A circuit level fault model for resistive opens and bridges
Z Li, X Lu, W Qiu, W Shi, DMH Walker
IEEE VLSI Test Symp, pp. 379--384, 2003

An O (nlogn) time algorithm for optimal buffer insertion
W Shi, Z Li
Proceedings of the 40th annual Design Automation Conference, pp. 580--585, 2003


2002

TETA: Transistor-level waveform evaluation for timing analysis
E Acar, F Dartu, L T Pileggi
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 21(5), 605--616, IEEE, 2002

Time-domain simulation of variational interconnect models
Emrah Acar, Sani Nassif, Ying Liu, Lawrence T Pileggi
Quality Electronic Design, 2002. Proceedings. International Symposium on, pp. 419--424

A linear-centric simulation framework for parametric fluctuations
Emrah Acar, S Nassif, L Pileggi
Proceedings of the conference on Design, automation and test in Europe, pp. 568, 2002

Method and system for short-circuit current modeling in CMOS integrated circuits
E Acar, R Arunachalam, S R Nassif
US Patent App. 20,040/117,169

Method and system for power node current waveform modeling
E Acar, S R Nassif
US Patent App. 20,040/054,974

A Delay Metric for RC Circuits based on the Weibull Distribution. IEEE/ACM Intl
F Liu, C Kashyap, CJ Alpert
Conference on Computer-Aided Design, pp. 620--624, 2002

PERI: a technique for extending delay and slew metrics to ramp inputs
CV Kashyap, CJ Alpert, F Liu, A Devgan
Proceedings of the 8th ACM/IEEE international workshop on …, 2002 - portal.acm.org

Free space management for cut-based placement
C J Alpert, G J Nam, P G Villarrubia
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 746--751

Early analysis tools for system-on-a-chip design
JA Darringer, RA Bergamaschi, S Bhattacharya, D Brand, A Herkersdorf, JK Morrell, II Nair, P Sagmeister, Y Shin
IBM Journal of Research and Development 46(6), 691--707, IBM, 2002

A Delay Metric for RC Circuits Based on the Weibull Distribution
F Liu, C Kashyap, CJ Alpert
International Conference on Computer Aided Design: …, 2002 - doi.ieeecomputersociety.org

Buffered Steiner Trees for Difficult Instances
CJ Alpert, G Gandham, M Hrkic, J Hu, AB Kahng, J …
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED …, 2002 - ieeexplore.ieee.org


2001

Assessment of true worst case circuit performance under interconnect parameter variations
E Acar, S Nassif, Y Liu, L T Pileggi
Quality Electronic Design, 2001 International Symposium on, pp. 431--436

Early Analysis Tools for System-on-a-Chip Design
Bergamaschi, S Bhattacharya, D Brand, J Darringer …
IBM Journal of Research and Development, 2001

A Steiner tree construction for buffers, blockages, and bays
CJ Alpert, G Gandham, J Hu, JL Neves, ST Quay, SS Sapatnekar
IEEE Transactions on Computer-Aided Design 20(4), 556--562, 2001

Design and development paradigm for industrial formal verification CAD tools
N Krishnamurthy, M S Abadir, A K Martin, J A Abraham
IEEE Design \& Test of Computers 18(4), 26--35, Institute of Electrical and Electronics Engineers, Inc, 445 Hoes Ln, Piscataway, NJ, 08854-1331, USA,, 2001

Interconnect Synthesis Without Wire Tapering
CJ Alpert, A Devgan, JP Fishburn, ST Quay
IEEE Transactions on Computer-Aided Design of Integrated …, 2001 - doi.ieeecomputersociety.org


2000

Hypergraph partitioning with fixed vertices
CJ Alpert, AE Caldwell, AB Kahng, IL Markov
Computer-Aided Design of Integrated Circuits and Systems, …, 2000 - ieeexplore.ieee.org

Datapath routing based on a decongestion metric
S Raman, SS Sapatnekar, CJ Alpert
Proceedings of the 2000 international symposium on Physical …, 2000 - portal.acm.org

Hypergraph Partitioning with Fixed Vertices
CJ Alpert, AE Caldwell, AB Kang, IL Markov
IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED …, 2000 - citeseer.ist.psu.edu

Buffer library selection
CJ Alpert, RG Gandham, JL Neves, ST Quay
IEEE International Conference on Computer Design, 2000 - doi.ieeecs.org

An" Effective" Capacitance Based Delay Metric for RC Interconnect
CV Kashyap, CJ Alpert, A Devgan
IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 2000 - doi.ieeecomputersociety.org

Transformational placement and synthesis
W Donath, P Kudva, L Stok, P Villarrubia, L Reddy, …
Design, Automation and Test in Europe Conference and …, 2000 - ieeexplore.ieee.org

A two moment RC delay metric for performance optimization
CJ Alpert, A Devgan, C Kashyap
Proceedings of the 2000 international symposium on Physical …, 2000 - portal.acm.org

EDA in IBM : past, present, and future
J Darringer, E Davidson, DJ Hathaway, B Koenemann, …
IEEE Transactions on Computer-Aided Design of Integrated …, 2000 - ieeexplore.ieee.org

LSS: a system for production logic synthesis
J A Darringer, D Brand, J V Gerbi, W H Joyner, L Trevillyan
IBM Journal of Research and Development, Vol 44 44(1-2), 157--165, IBM Corp., 2000


1999

Logics for Digital Circuit Verification: Theory, Algorithms, and Applications
Geert Janssen
Ph.D. Thesis Eindhoven University, ISBN 90-386-1560-4, Februari 24, 1999

Partitioning with terminals: a new problem and new benchmarks
CJ Alpert, AE Caldwell, AB Kahng, IL Markov
Proceedings of the 1999 international symposium on Physical …, 1999 - portal.acm.org

Buffer insertion with accurate models for gate and interconnect delay
C Alpert, A Devghan, S Quay
Proceedings of DAC, 1999

Is wire tapering worthwhile?
CJ Alpert, A Devgan, ST Quay
Proceedings of the 1999 IEEE/ACM international conference on …, 1999 - portal.acm.org

Spectral partitioning with multiple eigenvectors
CJ Alpert, AB Kahng, SZ Yao
Discrete Applied Mathematics, 1999 - Elsevier

Buffer Insertion with Accurate Gate and Interconnect Delay Computation
CJ Alpert, A Devgan, ST Quay
DESIGN AUTOMATION CONFERENCE, 1999 - doi.ieeecomputersociety.org

Buffer insertion for noise and delay optimization
C J Alpert, A Devgan, S T Quay
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18(11), 1633--1645, 1999


1998

A Study of BDD Performance in Model Checking
B Yang, RE Bryant, DR OHallaron, A Biere, O …
Formal Methods in Computer Aided Design, 1998

The ISPD circuit benchmark suite
CJ Alpert
ACM International Symposium on Physical Design, pp. 80--85, 1998

Design constraints in symbolic model checking
M Kaufman, A Martin, C Pixley
Computer Aided Verification, pp. 477--487, 1998

A performance study of BDD-based model checking
B Yang, RE Bryant, DR O'Hallaron, A Biere, O …
Lecture Notes in Computer Science, 1998 - Springer

The ISPD98 circuit benchmark suite
CJ Alpert
Proceedings of the 1998 international symposium on Physical …, 1998 - portal.acm.org

Multilevel circuit partitioning
C J Alpert, J H Huang, A B Kahng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(8), 655--667, 1998


1997

Splitting Orderings into Multi-way Partitionings to Minimize the Maximum Diameter
CJ Alpert, AB Kahng
Journal of Classification,(14), 51--74, 1997

Splitting an ordering into a partition to minimize diameter
C J Alpert, A B Kahng
Journal of Classification 14(1), 51--74, Springer, 1997

Quadratic placement revisited
CJ Alpert, T Chan, D J H Huang, I Markov, K Yan
1997 - computer.org, ACM

Faster minimization of linear wirelength for global placement
C J Alpert, T F Chan, D J H Huang, A B Kahng, I L Markov, P Mulet, K Yan
Proceedings of the 1997 international symposium on Physical design, pp. 11

Wire Segmenting for Improved Buffer Insertion
C Alpert, A Devgan
DESIGN AUTOMATION CONFERENCE, 1997 - doi.ieeecomputersociety.org


1996

Multi-way graph and hypergraph partitioning
C J Alpert
1996 - portal.acm.org, University of California, Los Angeles

A general framework for vertex orderings with applications tocircuit clustering
CJ Alpert, AB Kahng
IEEE transactions on very large scale integration (VLSI) systems 4(2), 万方数据资源系统, 1996

A hybrid multilevel/genetic approach for circuit partitioning
CJ Alpert, LW Hagen, AB Kahng
Circuits and Systems, 1996., IEEE Asia Pacific Conference on, 1996 - ieeexplore.ieee.org


1995

Prim-dijkstra tradeoffs for improved performance-driven global routing
CJ Alpert, TC Hu, JH Huang, AB Kahng, D Karger
IEEE Transactions on CAD 14(7), 890--896, 1995

Application of BDDs in Formal Verification
G Janssen
Proceedings of the 22 nd International School and Conference …, 1995 - ics.ele.tue.nl

Exploiting structural similarities in a BDD-based verification method
CAJ Van Eijk, G Janssen
Lecture Notes in Computer Science, 1995 - Springer

Multiway partitioning via geometric embeddings, orderings, and dynamic programming
C J Alpert, A B Kahng
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 14(11), 1342--1358, 1995

Prim-Dijkstra tradeoffs for improved performance-driven routingtree design
CJ Alpert, TC Hu, JH Huang, AB Kahng, D Karger
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14(7), 890--896, 1995

Spectral partitioning: the more eigenvectors, the better
C J Alpert, S Z Yao
32nd Conference on Design Automation, 1995, pp. 195--200

Recent directions in netlist partitioning: a survey* 1
C J Alpert, A B Kahng
INTEGRATION, the VLSI journal 19(1-2), 1--81, Elsevier, 1995


1994

A general framework for vertex orderings, with applications to netlist clustering
CJ Alpert, AB Kahng
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, pp. 67

Multi-way partitioning via spacefilling curves and dynamic programming
CJ Alpert, AB Kahng
Proceedings of the 31st annual Design Automation Conference, pp. 657, 1994


1993

Geometric embeddings for faster and better multi-way netlist partitioning
CJ Alpert, AB Kahng
Proceedings of the 30th international Design Automation Conference, pp. 743--748, 1993

A direct combination of the Prim and Dijkstra constructions for improved performance-driven global routing
CJ Alpert, TC Hu, JH Huang, AB Kahng
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 1869--1869, 1993


1989

Circuit Modelling and Animated Interactive Simulation in Escher+
Geert Janssen
Proceedings SCS European Simulation Multiconference, 1989


1988

A new look at logic synthesis
JA Darringer, WHJ Joyner
25 years of DAC Papers on Twenty-five years of electronic design automation, 1988

The application of program verification techniques to hardware verification
JA Darringer
25 years of DAC Papers on Twenty-five years of electronic design automation, 1988


1987

Logic synthesis
D BRAND
Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, 301, Taylor \& Francis US, 1987


1986

Network Description & Modelling Language - NDML
Geert Janssen
The Integrated Circuit Design Book, The Integrated Circuit Design Book (ed. E P. DeWilde), Delft University Press, 1986


1985

Production logic synthesis
J Darringer, D Brand, W H Joyner Jr, L Trevillyan, J V Gerbi
Proceedings of the 1985 ACM thirteenth annual conference on Computer Science, pp. 16


1984

Automated Logic Synthesis
JA Darringer
Lecture Notes In Computer Science; Vol. 163, 1984 - Springer


1981

Logic synthesis through local transformations
JA Darringer, WHJ Jr., CL Berman, L Trevillyan
IBM Journal of Research and Development, 1981 - research.ibm.com


1978

Applications of symbolic execution to program testing
JA Darringer, JC King
Computer, 1978 - ieeexplore.ieee.org


1968

A language for the description of digital computer processors
JA Darringer
Proceedings of the 5th annual workshop on Design automation, 1968 - portal.acm.org