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Logic Technologies Publications



2017

Design intent optimization at the beyond 7nm node: the intersection of DTCO and EUVL stochastic mitigation techniques
Crouse, Michael and Liebmann, Lars and Plachecki, Vince and Salama, Mohamed and Chen, Yulu and Saulnier, Nicole and Dunn, Derren and Matthew, Itty and Hsu, Stephen and Gronlund, Keith and others
SPIE Advanced Lithography, pp. 101480H--101480H, 2017
Abstract

Single-expose patterning development for EUV lithography
De Silva, Anuja and Petrillo, Karen E and Meli, Luciana and Shearer, Jefferey C and Beique, Genevieve and Sun, Lei and Seshadri, Indira and Oh, Taehwan and Ayothi, Ramakrishnan and Saulnier, Nicole and others
SPIE Advanced Lithography, pp. 101431G--101431G, 2017
Abstract

Driving down defect density in composite EUV patterning film stacks
Meli, Luciana and Petrillo, Karen and De Silva, Anuja and Arnold, John and Felix, Nelson and Johnson, Richard and Murray, Cody and Hubbard, Alex and Durrant, Danielle and Hontake, Koichi and others
SPIE Advanced Lithography, pp. 101430Y--101430Y, 2017
Abstract

Applications of clustering model to bimodal distributions for dielectric breakdown
Wu, Ernest Y and Bolam, Ronald and Filippi, Ronald and Stathis, James H and Li, Baozhen and Kim, Andrew
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 35(1), 01A112, AVS, 2017
Abstract

First Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially-Grown Emitter/Collector Regions
P. Hashemi, J.-B. Yau, K.K. Chan, T.H. Ning, G.G. Shahidi
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, IEEE, 2017

High Performance and Low Leakage Current InGaAs-on-Silicon FinFETs with 20 nm Gate Length
X. Sun, C. Demic, C.-W. Cheng, A. Majumdar, Y. Sun, E. Cartier, R. Bruce, M. Frank, H. Miyazoe, K.-T. Shiu, S. Lee, J. Rozen, J. Patel, T. Ando, W.-B. Song, M. Lofaro, M. Krishnan, B. Obrodovic, K.-T. Lee, H. Tsai, W.-E. Wang, W. Spratt, K. Chan, S. Lee, P. Hashemi, M. Khojaste
VLSI Tech. Symp., 2017

Comprehensive analysis of line-edge and line-width roughness for EUV lithography
Ravi K. Bonam, Chi-Chun Liu, Mary Breton, Stuart Sieg, Indira Seshadri, Nicole Saulnier, Jeffrey Shearer, Gangadhara R. Muthinti, Raghuveer Patlolla, Huai Huang
Extreme Ultraviolet (EUV) Lithography VIII, SPIE Advanced Lithography, 2017

An OCD perspective of line edge and line width roughness metrology
Ravi K. Bonam, Gangadhara R. Muthinti, Mary Breton, Chi-Chun Liu, Stuart Sieg, Indira Seshadri, Nicole Saulnier, Jeffrey Shearer
Metrology, Inspection, and Process Control for Microlithography XXXI, SPIE Advanced Lithography, 2017

Electrical test prediction using hybrid metrology and machine learning
Mary Breton, Robin Chao, Gangadhara Raja Muthinti, Abraham A. de la Pena, Jacques Simon, Aron J. Ceplar, Matthew J. Sendelbach, John Gaudiello, Hao Tang, Susan Emans, Michael Shifrin, Yoav Etzioni, Ronen Urenski, Wei T. Lee
Metrology, Inspection, and Process Control for Microlithography XXXI, SPIE Advanced Lithography, 2017


2016

EUV patterning successes and frontiers
Felix, Nelson and Corliss, Dan and Petrillo, Karen and Saulnier, Nicole and Xu, Yongan and Meli, Luciana and Tang, Hao and De Silva, Anuja and Hamieh, Bassem and Burkhardt, Martin and others
SPIE Advanced Lithography, pp. 97761O--97761O, 2016
Abstract

EUV Lithography: Co-optimization of Process and Computation Lithography Solutions (Invited Talk)
Nicole Saulnier
60th International Conference on Electron, Ion, and Photo Beam Technology and Nanofabrication: Optical and EUV Lithography, 2016
Abstract

Comparison of left and right side line-edge roughness in lithography
Sun, Lei and Saulnier, Nicole and Beique, Genevieve and Verduijn, Erik and Wang, Wenhui and Xu, Yongan and Tang, Hao and Chen, Yulu and Kim, Ryoung-han and Arnold, John and others
SPIE Advanced Lithography, pp. 977822--977822, 2016
Abstract

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process
Hitomi, Keiichiro and Halle, Scott and Miller, Marshal and Graur, Ioana and Saulnier, Nicole and Dunn, Derren and Okai, Nobuhiro and Hotta, Shoji and Yamaguchi, Atuko and Komuro, Hitoshi and others
Journal of Micro/Nanolithography, MEMS, and MOEMS 15(3), 034002--034002, International Society for Optics and Photonics, 2016
Abstract

EUV implementation of assist features in contact patterns
Jiang, Fan and Raghunathan, Ananthan and Burkhardt, Martin and Saulnier, Nicole and Tritchkov, Alexander and Jayaram, Srividya and Word, James
SPIE Advanced Lithography, pp. 97761U--97761U, 2016
Abstract

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Xie, R and Montanini, P and Akarvardar, K and Tripathi, N and Haran, B and Johnson, S and Hook, T and Hamieh, B and Corliss, D and Wang, J and others
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 2--7
Abstract

Self heating reduction for analog RF device for dielectric isolated Bulk FINFET
Soon-Cheon Seo, TENKO YAMASHITA, Balasubramanian Pranatharthiharan, Injo OK, Charan Surisetty

EUV patterning successes and frontiers
Nelson Felix, Dan Corliss, Karen Petrillo, Nicole Saulnier, Yongan Xu, Luciana Meli, Hao Tang, Anuja De Silva, Bassem Hamieh, Martin Burkhardt, Yann Mignot, Richard Johnson, Chris Robinson, Mary Breton, Indira Seshadri, Derren Dunn, Stuart Sieg, & others
Extreme Ultraviolet (EUV) Lithography VII, pp. 97761O--97761O, SPIE Advanced Lithography, 2016

Hot carrier effect in ultra-scaled replacement metal gate Si ix Ge x channel p-FinFETs
Wang, Miaomiao and Miao, Xin and Stathis, James H and Southwick, Richard and Linder, Barry P and Liu, Derrick and Bao, Ruqiang and Watanabe, Koji
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 15--4
Abstract

Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations
Bonilla, Griselda and Li, Baozhen and Linder, Barry P and Stathis, James H and Wu, Ernest Y and Zhao, Kai
US Patent 9,287,185
Abstract

Fundamental statistical properties of reconstruction methodology for TDDB with variability in BEOL/MOL/FEOL applications
Wu, Ernest and Stathis, James and Li, Baozhen and Kim, Andrew and Linder, Barry and Bolam, Ronald and Bonilla, Griselda
Reliability Physics Symposium (IRPS), 2016 IEEE International, pp. 3A--1
Abstract

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, X. Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonte, S. Fan, L
2016 IEEE International Electron Devices Meeting (IEDM), pp. 2.7.1-2.7.4

Hybrid Fin Reveal for Tight Fin Pitch Technologies
Peng Xu, Peng Wang, Zhenxing Bi, Thamarai Devarajan, Bhaskar Nagabhirava, Adarsh Basavalingappa, Fee Li Lie, Jay Strane, Muthumanickam Sankarapandian, Sanjay Mehta, Richard Conti, Michael Goss, Donald Canaperi, Dechao Guo, Sivananda Kanakasabapathy
AVS 63rd International Symposium & Exhibition 2016
Abstract

Dual Channel Si/SiGe Fin Patterning for 10 nm Node and Beyond
F.L. Lie, E. Miller, Peng Xu, S. Sieg, M. Sankarapandian, S. Schmitz, P. Friddle, G. Karve, J. Strane, K.Y. Lim, K. Akarvardar, M.G. Sung, S. Kanakabasapathy
AVS 63rd International Symposium & Exhibition 2016, 2016


2015

Towards production ready processing with a state-of-the-art EUV cluster
Petrillo, Karen and Saulnier, Nicole and Johnson, Richard and Meli, Luciana and Robinson, Chris and Koay, Chiew-seng and Felix, Nelson and Corliss, Daniel and Colburn, Matthew and Saito, Takashi and others
SPIE Advanced Lithography, pp. 94220R--94220R, 2015
Abstract