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Computer Architecture - University Collaborations



Carnegie-Mellon University
       Completed   Babak Falsafi
   Tom Puzak
   
Proactive memory hierarchies based on last touch memory access model

Cornell University
       Completed   Prof. David H. Albonesi
   Alper Buyuktosunoglu
Pradip Bose
   
Complexity Effective Multiple Clock Domain Processor Design

Cornell University
       Completed   Keshav Pingali
   Calin Cascaval
   
Continuous Program Optimization
  ·  Project Page

Dartmouth College
       Completed   Thomas H. Cormen
   Calin Cascaval
   
Out-of-core computation
  ·  Project Page

Harvard University
       Completed   David Brooks
   Victor Zyuban
Zhigang Hu
   
  • Development of Hierarchical Power and Timing Models for Architectural Power-Performance Analysis
  • Integrated Power-Performance Modeling Toolkit for PPC Architectures

  • Massachusetts Institute of Technology
           Completed   Arvind
    Krste Asanovic
       Balaram Sinharoy
       
    Energy-Efficient High-Performance Computing
      ·  Project Page

    Princeton University
           Completed   Margaret Martonosi
       Alper Buyuktosunoglu
    Pradip Bose
       
    Workload Power/Performance Phase Behavior Characterization, Detection and Prediction
      ·  Project Page

    Seoul National University
           Completed   Soo-Mook Moon
       Kemal Ebcioglu
    Erik Altman
       
    JAVA JIT compilation for ILP

    Technische Universität Wien
           Completed   Andreas Krall
       Kemal Ebcioglu
    Michael Gschwind
       
    Advanced Loop Scheduling

    Universitat Politècnica de Catalunya
           Completed   Eduard Ayguade
       Jose Moreira
       
    OpenMP compiler for IBM BlueGene architecture

    Universitat Politècnica de Catalunya
           Completed   Mateo Valero
       Bilha Mendelson
       
    VMX^2: 2-dimensional vector multimedia extensions

    Universitat Politècnica de Catalunya
           Completed   Mateo Valero
    Alex Ramirez
       Bilha Mendelson
    Jaime Moreno
       
    Co-processor architectures to exploit data-level parallelism

    University of California San Diego
           Completed   Dean Tullsen
       Pradip Bose
       
    Complexity and Power-Efficient Processor Architecture Design Via Multithreading

    University of Illinois at Urbana-Champaign
           Completed   Josep Torrellas
    Jose Martinez
       K. Ekanadham
    Pratap Pattnaik
       
    Hardware aids for speculative execution of loop iterations

    University of Illinois at Urbana-Champaign
           Completed   Josep Torrellas
    David Padua
       Calin Cascaval
       
    Programming languages, Continuous Program Optimization, Thread level speculation
      ·  Project Page

    University of Illinois at Urbana Champaign
           Completed   Sanjay Patel
       Jude Rivers
       
  • Architecture Technologies for the 2014
  • Graphite: New Frontiers in Compiler/Architecture Interaction

  • University of Maryland College Park
           Completed   Manoj Franklin
       Krishnan Kailas
       
    Co-Designed Virtual Machines for Performance, Power, and Fault Tolerance

    University of Michigan
           Completed   Ed Davidson
       Pradip Bose
       
    Workload characterization and scalability analysis of chip multiprocessors

    University of Michigan
           Completed   Steven Reinhardt
       Jude Rivers
       
    Architectural Enhancements for Network I/O

    University of Michigan
           Completed   Ed Davidson
    Trevor Mudge
    Gary Tyson
    Steve Reinhardt
       Tom Puzak
    Mark Charney
    Phil Emma
       
    Binary recompilation, memory system architecture

    University of Minnesota-Twin Cities
           Ongoing   Antonia Zhai
       Kathryn O'Brien
       
    Hardware and Software Support for Flexible and Scalable Speculatively Parallel Execution on Multicore Processors

    University of Notre Dame
           Completed    Prof. Peter Kogge
    Alexei Koudriavtsev
       Victor Zyuban
       
    Estimating Energy-Efficiency of SIMD Processors

    University of Rochester
           Completed   Sandhya Dwarkadas
       Evelyn Duesterwald
       
  • An Integrated Hardware/Software Approach to On-Line Power-Performance Optimization
  • Characterizing and Exploiting Program Behavior and Its Variability for On-Line Power-Performance Optimization

  • University of Rochester
           Completed   David Albonesi
       Pradip Bose
       
    Power-aware microarchitecture for emerging applications

    University of Rochester
           Completed   David Albonesi
       Alper Buyuktosunoglu
       
    Multiple Clock Domain Processors and Systems

    University of Southern California
           Completed   Michel Dubois
       Ashwini Nanda
       
    Memory system architecture for multiprocessors

    University of Southern California
           Ongoing   Murali Annavaram
       Pradip Bose
       
    Bullet Proofing Processors Using 3D Stacked Variability Monitors

    University of Texas at Austin
           Ongoing   Yale Patt
       Philip Emma
       
    Microarchitecture Characteristics of the Year 2014; overcoming the problems that come with one billion transistor, 10 GHz chips

    University of Texas at Austin
           Completed   Yale Patt
       Thomas R. Puzak
       
    Performance analysis and Computer Architecture

    University of Texas at Austin
           Completed   Doug Burger
       Balaram Sinharoy
       
    Polymorphic Processors
      ·  Project Page

    University of Texas at Austin
           Ongoing   Derek Chiou
       Volker Strumpen
       
    PowerPC on RAMP

    University of Toronto
           Ongoing   Moshovos, Andreas
       Vijayalakshmi Srinivasan
       
    Making the Best of Multi-Megabyte Memory Hierarchies via Coarse-Grain Tracking and Management and via Predictor Virtualization

    University of Virginia
           Completed   Kevin Skadron
       Zhigang Hu
       
    Accounting for Thermal, Leakage, and other Physical Phenomena in SMT and CMP Architecture

    University of Wisconsin-Madison
           Completed   Jim Smith
       Ravi Nair
       
    Whole-system virtual machine architectures and implementations




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    Upcoming Seminars

    • November 4, 2010
      Architecture, Design, and Implementation of a 3D-IC Many-core Processor, Prof. Hsien-Hsin S. Lee, Georgia Institute of Technology.
    • November 5, 2010
      Understanding the memory systems of a modern NUMA Processor, Prof. Thomas Gross, ETH Zurich.

    A complete list of recent seminars can be found here.