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Computer Architecture


The following patents are issued since 2010 in Computer Architecture and related areas.

Patents issued in 2014

  • Dynamically Maintaining Coherency Within Live Ranges Of Direct Buffers,7/8/2014,Patent US8776034,John O'Brien, Tong Chen, Tao Zhang
  • Dynamically Rewriting Branch Instructions In Response To Cache Line Eviction,7/15/2014,Patent US8782381,Mark Nutter, John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs, Tong Chen
  • Path-Sensitive Analysis For Reducing Rollback Overheads,7/22/2014,Patent US8789025,Mark Yamashita, Kai-Ting Wang, Xiaotong Zhuang, John
  • Prefetching Irregular Data References For Software Controlled Caches,6/24/2014,Patent US8762968,Marc Gonzalez Tallada, Zehra Sura, Tong Chen, Tao Zhang
  • Method And System For Efficient Emulation Of Multiprocessor Address Translation On A Multiprocessor Host,5/6/2014,Patent US8719548,John O'Brien, Kathryn O'Brien, Erik Altman, Daniel Prener, Peter H Oden, Ravi Nair, Sumedh Sathaye
  • Hybrid Caching Techniques And Garbage Collection Using Hybrid Caching Techniques,5/27/2014,Patent US8738859,Chen-Yong Cher, Michael Gschwind
  • Management Of Conditional Branches Within A Data Parallel System,5/13/2014,Patent US8726252,Ulrich Weigand, Ira Rosen, Alexandre Eichenberger, Dorit Nuzman, Ayal Zaks, Brian Flachs
  • Semiconductor Chip Stacking For Redundancy And Yield Improvement,4/1/2014,Patent US8686559,Philip Emma, Mike Ignatowski, Kerry Bernstein
  • Rewriting Branch Instructions Using Branch Stubs,4/29/2014,Patent US8713548,Mark Nutter, John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs, Tong Chen
  • Speculative Thread Execution And Asynchronous Conflict Events,4/1/2014,Patent US8689221,Kai-Ting Wang, Xiaotong Zhuang, John O'Brien, Thomas Gooding
  • Memory System With Dynamic Refreshing,4/22/2014,Patent US8705307,Warren Maule, Hillery Hunter, Joab Henderson, Jeff Stuecheli
  • Semiconductor Chip Repair By Stacking Of A Base Semiconductor Chip And A Repair Semiconductor Chip,3/25/2014,Patent US8679861,Pradip Bose, Victor Zyuban, Eren Kursun, Jude Rivers
  • Enhanced Modularity In Heterogeneous 3D Stacks,3/25/2014,Patent US8677613,Eren Kursun, Philip Emma, Jude Rivers
  • Building Approximate Data Dependencies With A Moving Window,3/4/2014,Patent US8667260,Kai-Ting Wang, Xiaotong Zhuang, John O'Brien, Kathryn O'Brien, Alexandre Eichenberger
  • Memory Bus Write Prioritization,3/25/2014,Patent US8683128,Benjiman Goodman, William Starke, David Daly, Hillery Hunter, Jeff Stuecheli
  • Adaptive Workload Based Optmizations To Mitigate Current Delivery Limitations In Integrated Circuits,3/25/2014,Patent US8683418,Pradip Bose, Alper Buyuktosunoglu, Jeonghee Shin, Moinuddin Qureshi, Darringer, John A.
  • Complex Matrix Multiplication Operations With Data Pre-Conditioning In A High Performance Computing Architecture.,2/11/2014,Patent US8650240,Alexandre Eichenberger, John Gunnels, Michael Gschwind
  • Managing Multiple Speculative Assist Threads At Differing Cache Levels,2/18/2014,Patent US8656142,Yaoqing Gao, Tong Chen
  • On-Chip Power Proxy Based Architecture,2/11/2014,Patent US8650413,Michael Floyd, Pradip Bose, Alper Buyuktosunoglu, Maria Pesantez
  • Memory Bus Write Prioritization,2/4/2014,Patent US8645627,Benjiman Goodman, William Starke, David Daly, Hillery Hunter, Jeff Stuecheli
  • Method And System For Controlling Power In A Chip Through A Power-Performance Monitor And Control Unit,1/28/2014,Patent US8639955,Chen-Yong Cher, Pradip Bose, Alper Buyuktosunoglu, Prabhakar Kudva
  • Dynamically Rewriting Branch Instructions To Directly Target An Instruction Cache Location,1/7/2014,Patent US8627051,Nutter, Mark R., John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs, Tong Chen
  • Dynamically Rewriting Branch Instructions To Directly Target An Instruction Cache Location,1/14/2014,Patent US8631225,Nutter, Mark R., John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs, Tong Chen
  • Data Parallel Function Call For Determining If Called Routine Is Data Parallel,1/7/2014,Patent US8627043,Charles Johns, Nutter, Mark R., Alexandre Eichenberger, Brian Flachs
  • Data Parallel Function Call For Determining If Called Routine Is Data Parallel,1/7/2014,Patent US8627042,Charles Johns, Nutter, Mark R., Alexandre Eichenberger, Brian Flachs
  • Write-Through Cache Optimized For Dependence-Free Parallel Regions,1/7/2014,Patent US8627010,Alan Gara, Alexandre Eichenberger, Martin Ohmacht, Vijayalakshmi Srinivasan
  • Method And Apparatus For Performing Refresh Operations In High-Density Memories,1/21/2014,Patent US8635401,Benjiman Goodman, Stephen Powell, Hillery Hunter, John Dodson, Jeff Stuecheli
  • Dynamically Tune Power Proxy Architectures,1/21/2014,Patent US8635483,Michael Floyd, Pradip Bose, Emrah Acar, Alper Buyuktosunoglu, Maria Pesantez, Gregory Still, Bishop Brock

Patents issued in 2013

  • Semiconductor Chip Stacking For Redundancy And Yield Improvement,12/3/2013,Patent US8597960,Philip Emma, Mike Ignatowski, Kerry Bernstein
  • Coordinated Writeback Of Dirty Cachelines,12/24/2013,Patent US8615634,Benjiman Goodman, William Starke, David Daly, Hillery Hunter, Jeff Stuecheli
  • Hybrid Mechanism For More Efficient Emulation And Method Thereof,11/5/2013,Patent US8578351,John O'Brien, Kathryn O'Brien, Daniel Prener, Peter H Oden, Ravi Nair
  • Accepting Or Rolling Back Execution Of Instructions Based On Comparing Predicted And Actual Dependency Control Signals,11/19/2013,Patent US8589662,Victor Zyuban, John David Wellman, Erik Altman, Jude Rivers, Sumedh Sathaye, Michael Gschwind
  • Matrix Multiplication Operations With Data Pre-Conditioning In A High Performance Computing Architecture,11/5/2013,Patent US8577950,Alexandre Eichenberger, John Gunnels, Michael Gschwind
  • Low-Overhead Dynamic Thermal Management For Many-Core Cluster Architecture,11/26/2013,Patent US8595731,Pradip Bose, Eren Kursun, Philip Emma, Jude Rivers
  • Reducing Parallelism Of Computer Source Code,11/12/2013,Patent US8584103,John O'Brien, Uday Kumar Bondhugula, Yuan Zhao, Lakshminarayanan Renganarayana, Alexandre Eichenberger
  • Runtime Extraction Of Data Parallelism,11/12/2013,Patent US8583905,Charles Johns, Mark Nutter, Alexandre Eichenberger, Brian Flachs
  • Adaptive Multi-Bit Error Correction In Endurance Limited Memories,11/19/2013,Patent US8589762,Vijayalakshmi Srinivasan, Jude Rivers
    • Data Transfer Optimized Software Cache for Regular Memory References, 09/03/2013, Patent 8527974, John O'Brien, Kathryn O'Brien, Marc Gonzalez tallada*, Alexandre Eichenberger, Zehra Sura, Tong Chen, Tao Zhang
    • Three-dimensional (3D) Stacked Integrated Circuit Testing, 09/24/2013, Patent 8542030, Chen-Yong Cher, Eren Kursun*, Raphael Robertazzi, Gary Maier
    • Guarded, Multi-metric Resource Control for Safe and Efficient Microprocessor Managment, 09/03/2013, Patent 8527994, Pradip Bose, Alper Buyuktosunoglu, NITI MADAN
    • Executing TOUCHBHT Instruction to Pre-Fetch: Information to Prediction Mechanism for Branch with Taken History*, 08/27/2013, Patent 8521999, Thomas Puzak*, Philip Emma, Vijayalakshmi Srinivasan, Brian Prasky, Allan Hartstein
    • Checkpointing in Speculative Versioning Caches*, 08/27/2013, Patent 8521961, Alan Gara, Alexandre Eichenberger*, Martin Ohmacht, Michael Gschwind
    • STI: SPE SOFTWARE INSTRUCTION CACHE, 08/20/2013, Patent 8516230, Mark Nutter, John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs*, TONG CHEN
    • Rewriting Branch Instructions Using Branch Stubs, 08/27/2013, Patent 8522225, Mark Nutter, John O'Brien, Kathryn O'Brien, Brad Michael, Brian Flachs, TONG CHEN*
    • Write-through Cache Optimized For Dependence-free Parallel Regions, 08/20/2013, Patent 8516197, Alan Gara, Alexandre Eichenberger*, Martin Ohmacht, Vijayalakshmi Srinivasan
    • Vertical Power Budgeting And Shifting For Three-dimensional Integration*, 08/20/2013, Patent 8516426, Phillip Restle, Michael Floyd, Pradip Bose, EREN KURSUN*, Gary Carpenter, Michael Scheuermann
    • Method And Structure Of Using Simd Vector Architectures To Implement Matrix Multiplication*, 06/04/2013, Patent 8458442, Fred Gustavson*, Alexandre Eichenberger, John Gunnels, Michael Gschwind
    • Runtime Dependence-aware Scheduling Using Assist Thread*, 06/11/2013, Patent 8464271, Xiaotong Zhuang*, Kathryn O'Brien, Alexandre Eichenberger
    • Insertion Of Operation-and-indicate Instructions For Optimized SIMD Code*, 06/04/2013, Patent 8458684, Alan Gara, Alexandre Eichenberger*, Michael Gschwind
    • Parallelization Of Irregular Reductions Via Parallel Building And Exploitation Of Conflict-free Units Of Work At Runtime*, 06/18/2013, Patent 8468508, Xiaotong Zhuang, John O'Brien, Alexandre Eichenberger*, N
    • Detecting Task Complete Dependencies Using Underlying Speculative Multi-threading Hardware*, 06/18/2013, Patent 8468539, Xiaotong Zhuang*, John O'Brien, Kathryn O'Brien, Lakshminarayanan Renganarayana, Alexandre Eichenberger
    • Method And Apparatus For Efficient Inter-thread Synchronization For Helper Threads*, 06/18/2013, Patent 8468531, Valentina Salapura*, John O'Brien, ZEHRA SURA, Michael Gschwind
    • Computer Program Product For Managing Processing Resources*, 06/25/2013, Patent 8473723, Ronald Luijten*, Philip Stanley-Marbell, HILLERY HUNTER
    • Measuring Data Switching Activity in a Microprocessor*, 06/04/2013, Patent 8458501, Pradip Bose, Victor Zyuban, Alper Buyuktosunoglu*, Christopher Gonzalez, MOINUDDIN QURESHI
    • Method And Apparatus For Efficient Helper Thread State Initialization Using Inter-thread Register Copy*, 05/28/2013, Patent 8453076, Valentina Salapura*, John O'Brien, ZEHRA SURA, Michael Gschwind
    • Thread Speculative Execution and Asynchronous Conflict*, 05/07/2013, Patent 8438571, KAI-TING WANG, Xiaotong Zhuang*, John O'Brien, Thomas Gooding
    • Code Generation for Complex Arithmetic Reduction for Architectures Lacking Cross Data-Path Support*, 04/16/2012, Patent 8423979, Peng Zhao, ROCH ARCHAMBAULT, KAI-TING WANG, Alexandre Eichenberger*, Peng Wu
    • Processor Core Stacking for Efficient Collaboration*, 04/09/2013, Patent 8417917, EREN KURSUN*, Philip Emma, Vijayalakshmi Srinivasan, MOINUDDIN QURESHI
    • Task Assignment on Heterogeneous Three-Dimensional/Stacked Microarchitectures*, 04/16/2012, Patent 8424006, Hans Jacobson*, EREN KURSUN

Patents issued in 2012

    • System and Method for Garbage Collection in Heterogeneous Multiprocessor Systems*, 12/07/2012, Patent 5147280, John O'Brien, Kathryn O'Brien, Michael Gschwind*
    • Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design*, 12/07/2012, Patent 5147944, Todd Swanson*, Matthew Fernsler, Johny Srouji, Hans Jacobson
    • Single Instruction Multiple Data (SIMD) Code Generation for Parallel Loops Using Versioning and Scheduling*, 12/25/20xx, Patent 8341615, GUANSONG ZHANG, KAI-TING WANG*, RAUL SILVERA, Alexandre Eichenberger
    • Methods for Generating Code for an Architecture Encoding and Extended Register Specification*, 11/13/2012, Patent 8312424, Brett Olsson, John David Wellman, Robert Montoye*, Michael Gschwind
    • Method and Structure for Provably Fari Random Number Generator*, 11/13/2012, Brian Monwai, Krishnan Kailas*, Viresh Paruthi
    • Hybrid Caching Techniques and Garbage Collection Using Hybrid Caching Techniques, 11/13/2012, Patent 8312219, CHEN-YONG CHER*, Michael Gschwind
    • Power Management for Systems on a Chip*, 11/13/2012, Patent 8312305, CHEN-YONG CHER*, TEJAS KARKHANIS, Srinivasan Ramani
    • Method and Apparatus for Fast Synchronization and Out-of-Order Execution of Instructions in a Meta-Program Based Computing System*, 10/30/2012, Patent 8301870, Krishnan Kailas*
    • Computer Analysis and Runtime Coherency Checking*, 10/02/2012, Patent 8281295, John O'Brien, TONG CHEN*, HAI BO LIN, Tao Zhang
    • Systems and Methods for Thread Assignment and Core Turn-Off for Integrated Circuit Energy Efficiency and High-Performance*, 10/23/2012, Patent 8296773, Pradip Bose, EREN KURSUN*, Alper Buyuktosunoglu
    • Dynamically Maintaining Coherency Within Live Ranges of Direct Buffers*, 10/09/2012, Patent 8285670, John O'Brien, TONG CHEN, Tao Zhang*
    • Reducing Broadcasts in Multiprocessors*, 10/09/2012, Patent 8285969, Khubaib Khubaib, Vijayalakshmi Srinivasan, MOINUDDIN QURESHI*
    • Compiler Implemented Software Cache in Which Non-Aliased Explicitly Fetched Data are Excluded*, 07/03/2012, Patent 8214816, John O'Brien, Kathryn O'Brien, ZEHRA SURA, Byoungro So, TONG CHEN*, Tao Zhang
    • System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment, 07/03/2012, Patent 8214808, John O'Brien*, Kathryn O'Brien, Michael Day, Michael Gschwind
    • Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design*, 07/11/2012, Patent ZL200880102482.4, Todd Swanson*, Matthew Fernsler, Johny Srouji, Hans Jacobson
    • Runtime Dependence-Aware Scheduling Using Assist Threads, 07/03/2012, Patent 8214831, Xiaotong Zhuang*, Kathryn O'Brien, Alexandre Eichenberger
    • Predictive Power Gating with Optional Guard Mechanism, 07/10/2012, Patent 8219834, Pradip Bose*, Alper Buyuktosunoglu, Jayanta Basak
    • Two-Level Guarded Predictive Power Gating*, 07/10/2012, Patent 8219833, Pradip Bose*, Alper Buyuktosunoglu, Anita Lungu, Jayanta Basak
    • SIMD Code Generation in the Presence of Optimized Misaligned Data Reorganization*, 06/05/2012, Patent 8196124, KAI-TING WANG, Alexandre Eichenberger, Peng Wu
    • Virtualizing the Execution of Homogeneous Parallel Systems on Heterogeneous Multiprocessor Platforms*, 06/12/2012, Patent 8201165, Ravi Nair*
    • Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System*, 06/18/2012, Patent 1159407, CHEN-YONG CHER, Pradip Bose, Raymond C Yeung*, Alper Buyuktosunoglu, Wolfram Sauer, Robert Philhower, Ravi Nair, Michael Gschwind
    • Efficient Code Generation Using Loop Peeling for SIMD Loop Code with Multiple Misaligned Statements*, 05/01/2012, KAI-TING WANG, Alexandre Eichenberger, Peng Wu
    • Wave Pipeline with Selectively Opaque Register Stages*, 05/08/2012, Hans Jacobson*
    • Managing Position Independent Code Using a Software Framework*, 02/28/2012, Patent 8126957, Mark Nutter, Michael Gowen, John O'Brien, Barry Minor*
    • Method and System for Controlling Power in a Chip Through a Power-Performance Monitor and Control Unit*, 02/07/2012, Patent 8112642, CHEN-YONG CHER, Pradip Bose, Alper Buyuktosunoglu*, Prabhakar Kudva
    • Hybrid Mechanism for More Efficient Emulation and Method Therefor, 01/31/2012, Patent 8108843, John O'Brien, Kathryn O'Brien, Daniel Prener, Peter H Oden, Ravi Nair*
    • Method and System for Soft Error Recovery During Processor Execution*, 01/31/2012, Patent 8108714, Pradip Bose, Victor Zyuban, Jude Rivers*
    • Structure for Implementing Dynamic Refresh protocols for Dram Based Cache*, 01/31/2012, Patent 8108609, Philip Emma, Erik Hedberg, John Barth Jr, Peter Sandon, Arnold Tran, Vijayalakshmi Srinivasan*, HILLERY HUNTER
    • Modeling System-Level Effects of Soft Errors*, 01/03/2012, Patent 8091050, Pradip Bose, John David Wellman, Pia Sanda, Jude Rivers*, Prabhakar Kudva
    • Dynamic Translation in the Presence of Intermixed Code and Data*, 01/24/2012, Patent 8103850, KEVIN STOODLEY, Ravi Nair*

Patents issued in 2011

    • Reducing Cache Pollution of Software Controlled Cache, 11/08/2011, Patent 8055849, Marc Gonzalez Tallada, ZEHRA SURA*, TONG CHEN, Tao Zhang
    • System and Method for Advanced Polyhedral Loop Transformations of Source Code in a Compiler, 11/15/2011, Patent 8060870, John O'Brien, Kathryn O'Brien, Nicolas Vasilache, Alexandre Eichenberger*
    • Stable Transitions in the Presence of Conditionals for an Advanced Dual-Representation Polyhedral Loop Transformation Framework, 11/08/2011, Patent 8056065, John O'Brien, Kathryn O'Brien, Nicolas Vasilache, Alexandre Eichenberger*
    • Three-Dimentional Cascaded Power Distribution in a Semiconductor Device*, 11/08/2011, Patent 8053819, Mark Ritter, Philip Emma, Paul Coteus, Kerry Bernstein*, Stephen Kosonocky, Ruchir Puri, Allan Hartstein
    • Framework for Integrated Intra- and Inter-Loop Aggregation of Contiguous Memory Access for SIMD Vectorization*, 11/08/2011, Patent 8056069, KAI-TING WANG, Alexandre Eichenberger, Peng Wu*
    • Dynamic Memory Architecture Employing Passive Expiration of Data, 9/13/2011, Patent 8020073, Philip Emma, William Reohr, Robert Montoye
    • Systems and Methods for Mutually Exclusive Activation of Microprocessor Resources to Control Maximum Power, 9/2/2011, Patent 4811879, Pradip Bose, Victor Zyuban, Hans Jacobson, Alper Buyuktosunoglu, Zhigang Hu, Vijayalakshmi Srinivasan
    • Method and System for Implementing Dynamic Refresh Protocols for Dram Based Cache, 9/20/2011, Patent 8024513, Philip Emma, Erik Hedberg, John Barth Jr, Peter Sandon, Arnold Tran, Vijayalakshmi Srinivasan, Hillery Hunter
    • Compiler Method for Eliminating Redundant Read-Modify-Write Code Sequences in Non-Vectorizable Code, 8/2011, Patent 8010957, John O'Brien, Kathryn O'Brien, Alexandre Eichenberger, Tong Chen
    • Cell Workload Partitioning in a Parallel System with Heterogeneous Alignment Constraints, 8/2011, Patent 8006238, John O'Brien, Kathryn O'Brien, Alexandre Eichenberger, Tong Chen
    • Augmenting of Automated Clustering Based Trade Sampling Methods by User Directed Phase Detection, 8/2011, Patent 8000953, Robert Bell Jr., Pattabi Seshadri, John David Wellman, Wen-Tzer Chen
    • Self-Tuning Power Management Techniques, 8/2011, Patent 8001405, Indira Nair, Alper Buyuktosunoglu, Gero Dittmann
    • Method and System of Multi-Core Microprocessor Power Management and Control Via Per-Chiplet, Programmable Power Modes, 8/2011, Patent 8001394, Michael Floyd, Pradip Bose, Alper Buyuktosunoglu
    • Iterative Write Pausing Techniques to Improve Read Latency of Memory Systems, 8/2011, Patent 8004884, Luis Lastras, Michele Franceschini, Vijayalakshmi Srinivasan, Moinuddin Qureshi
    • Method for Achieving Very High Bandwidth Between the Levels of a Cache Hierarchy in 3-Dimensional Structures and a 3-Dimensional Structure Resulting Therefrom, 7/26/2011, Patent 7986543, Philip Emma
    • Cache Line Replacement Techniques Allowing Choice of LFU or MFU Cache Line Replacement, 6/7/2011, Patent 7958311, Jaime Moreno, Richard Matick
    • Method and Apparatus for an Efficient Multi-Path Trace Cache Design, 6/7/2011, Patent 7958334, Vijayalakshmi Srinivasan, Jude Rivers, Galen Rasche
    • Compiler Method for Employing Multiple Autonomous Synergistic Processors to Simultaneously Operate on Longer Vectors of Data, 6/14/2011, Patent 7962906, John O'Brien, Kathryn O'Brien, Daniel Prener
    • Limiting Entries in Load Issued Premature Part if Load Reorder Queue Searched to Detect Invalid Retrieved Values Between Store Safe and Snoop Safe Pointers for the Congruence Class, 6/28/2011, Patent 7971033, Erik Altman, Vijayalakshmi Srinivasan
    • Limiting Entries in Load Reorder Queue Searched for Snoop Check to Between Coop Peril and Tail Pointers, 6/21/2011, Patent 7966478, Erik Altman, Vijayalakshmi Srinivasan
    • Method and System for Integrating SRAM and DRAM Architecture in Set Associative Cache, 6/14/2011, Patent 7962695, Marc Faucher, William Reohr, Peter Sandon, Arnold Tran, Vijayalakshmi Srinivasan, Hillery Hunter
    • Managing Speculative Assict Threads, 6/7/2011, Patent 2680597, Gennady Pekhimenko, ROCH ARCHAMBAULT, YAOQING GAO, RAUL SILVERA, KHALED MOHAMMED, John O'Brien, ZEHRA SURA, TONG CHEN
    • Method and System for Efficient Emulation of Multiprocessor Address Translation on a Multiprocessor Host, 5/2011, Patent 7953588, John O'Brien, Kathryn O'Brien, Erik Altman, Daniel Prener, Peter H Oden, Ravi Nair, Sumedh Sathaye
    • Method and Structure for Asynchronous Skip-Ahead in Synchronous Pipelines, 5/2011, Patent 7945765, Hans Jacobson, Philip Emma*, William Reohr, Allan Hartstein
    • Method and System for Providing an Improved Store-In Cache, 5/2011, Patent 7941728, Wing Kin Luk, Thomas Puzak, Philip Emma, Vijayalakshmi Srinivasan
    • Method and System of Peak Power Enforcement Via Autonomous Token-Based Control and Management, 4/19/2011, Patent 7930578, Pradip Bose, Victor Zyuban, Hans Jacobson, Alper Buyuktosunoglu, Zhigang Hu, Vijayalakshmi Srinivasan
    • Managing Multiple Speculative Assist Threads At Differing Cache Levels, 02/15/2011, Patent 2680601, Tong Chen, Yaoqing Gao
    • Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management, 2/8/2011, US Patent 7886172, Pradip Bose, Chen-Yong Cher, Hubertus Franke, Hendrik Hamann, Eren Kursun and Alan J. Weger
    • Cache Line Replacement Techniques Allowing Choice Of LFU Or MFU Cache Line Replacement, 1/11/2011, US Patent 7870341, Jaime Moreno, Richard Matick
    • Insuring Maximum Code Motion Of Accesses To DMA Buffers, 1/11/2011, US Patent 7870544, Daniel Brokenshire, John O'Brien
    • Adaptive Issue Queue For Reduced Power At High Performance, 1/4/2011, US Patent 7865747, Peter W Cook, Pradip Bose, Stanley E Schuster, David Brooks
    • Method And Apparatus To Extend The Number Of Instruction Bits In Processors With Fixed Length Instructions, In A Manner Compatible With Existing Code, 1/4/2011, US Patent 7865699, John David Wellman, Erik Altman, Daniel Prener, Dave Luick, Jude Rivers, Sumedh Sathaye, Michael Gschwind
    • Aligning Precision Converted Vector Data Using Mask Indicating Offset Relative To Element Boundary Corresponding To Precision Type, 1/4/2011, US Patent 7865693, Bruce Fleischer, Alexandre Eichenberger, Michael Gschwind
    • Method and System for Multiprocessor Emulation on a Multiprocessor Host System, 11/30/2010, US patent 7844446, John O'Brien, Kathryn O'Brien, Erik Altman, Daniel Prener, Peter H Oden, Ravi Nair, Sumedh Sathaye

Patents issued in 2010

  • Method and apparatus for application-specific dynamic cache placement, 11/16/2010, US Patent 7836256, Krishnan Kailas, Rajiv Ravindran, Zehra Sura.
  • Architectural Level Throughput Based Power Modeling Methodology And Apparatus For Pervasively Clock-Gated Processor Cores, 10/19/2010, US patent7818696, Pradip Bose, Malcolm Ware, Srinivasan Ramani, Ken Vu.
  • Processor Bus For Performance Monitoring With Digests, 10/19/2010, US patent 7818624, Ravi Nair, Hillery Hunter.
  • Digital Measuring System And Method For Integrated Circuit Chip Operating Parameters, 10/12/2010, US patent 7813815, Rick Rand, Philip Emma, Herschel Ainspan, Arthur Zingher.
  • DRAM Cache With On-Demand Reload, 9/28/2010, US patent 7805658, Wing Kin Luk, Ravi Nair.
  • Method For Constructing Autonomic Advisors And Learning Procedural Knowledge From Scored Examples, 9/21/2010, US patent 7801835, Daniel Oblinger, Lawrence Bergman, Tessa Lau, Vittorio Castelli, Prabhakar Kudva.
  • Method, System, And Computer Program Product For Path-Corrrelated Indirect Addres Predictions, 9/14/2010, US patent 7797521, Richard Eickemeyer, Robert Philhower, Ravi Nair, Michael Gschwind.
  • Implementing Instruction Set Architectures With Non-Contiguous Register File Specifiers, 9/7/2010, US patent 7793081, Brett Olsson, John David Wellman, Robert Montoye, Michael Gschwind.
  • Compiler Implemented Software Cache Method In Which Non Aliased Explicity Fetched Data Are Excluded, 8/24/2010, US patent 7784037, John O'Brien, Kathryn O'Brien, Zehra Sura, Byoungro So, TONG CHEN, Tao Zhang.
  • Method And Apparatus For Preventing Soft Error Accumulation In Register Arrays, 8/10/2010, US patent 7774654, Balaram Sinharoy, Pradip Bose, Victor Zyuban, Jude Rivers.
  • Performing Useful Computations While Waiting For A Line In A System With A Software Implemented Cache, 7/27/2010, US patent 7765360, John O'Brien, Kathryn O'Brien.
  • Bounded Starvation Checking Of An Arbiter Using Formal Verification, 7/6/2010, US patent 7752369, Brian Monwai, Krishnan Kailas, Viresh Paruthi.
  • State Machine Based Filtering Of Non-Dominant Branches To Use A Modified Gshare Scheme, 6/29/2010, US patent 7747845, Brian Prasky, Moinuddin Qureshi.
  • Efficient Generation Of Simd Code In Presence Of Multi-Threading And Other False Sharing Conditions And In Machines Having Memory Protection Support, 6/1/2010, US patent 7730463, Peng Zhao, KAI-TING WANG, Alexandre Eichenberger, Peng Wu.
  • Compact Representation Of Instruction Execution Path History, 5/25/2010, US patent 7725692,Ravi Nair.
  • Alignment Of Cache Fetch Return Data Relative To A Thread, 5/25/2010, US patent 7725659, Hans Jacobson, Robert Philhower, Michael Gschwind.
  • Three Dimensional Integrated Circuit And Method Of Design, 5/25/2010, US patent 7723207, David Kung, Kathryn Guarini, Mark Lavin, Meikei Ieong, Syed M Alam, Ibrahim Elfadel, Prabhakar Kudva.
  • Method For The Asynchronous Arbitration Of A High Frequency Bus In A Long Latency Environment, 5/25/2010, US patent 7724759, Ferenc Bozso, Sampath Purushothaman, Satya Nitta, Philip Emma, Bruce Furman.
  • System, Method And Computer Program Product For Executing A Cache Replacement Algorithm, 5/4/2010, US patent 7711904, Thomas Puzak, Daniel N Lynch, Philip Emma.
  • Method And System For Tracking Instruction Dependency In An Out Of Order Processor, 5/4/2010, US patent 7711929, William Burky, Krishnan Kailas.
  • System And Method For Predicting A Hardware And/Or Software Metrics In A Computer System Using Models, 4/13/2010, US patent 7698249, Alper Buyuktosunoglu, Ruhi Sarikaya.
  • 3-Dimensional Integrated Circuit Architecture, Structure And Method For Fabrication Thereof, 4/6/2010, US patent 7692944, Philip Emma, Paul Coteus, Kerry Bernstein.
  • Interlocked Synchronous Pipeline Clock Gating, 3/23/2010, US patent 7685457, Peter W Cook, Pradip Bose, Hans Jacobson, Stanley E Schuster, Prabhakar Kudva.
  • Structure Comprising 3-Dimensional Integrated Circuit Architecture Circuit Structure, And Instructions For Fabrication Thereof, 3/23/2010, US patent 7684224, Philip Emma, Paul Coteus, Kerry Bernstein.
  • Logic Block Timing Estimation Using Conesize, 3/9/2010, US patent 7676779, Mark Mayo, Reinaldo A Bergamaschi, Sean Carey, Matthew E Mariani, Ruchir Puri, Brian Curran, Prabhakar Kudva.
  • Effective Delayed, Minimized Switching, Btb Write Via Recent Entry Queue That Has The Ability To Delay Decode, 3/9/2010, US patent 7676663, Thomas Puzak, Brian Prasky, Allan Hartstein.
  • Method And System For Versioning Codes Based On Relative Alignment For Single Instruction Multiple Data Units, 3/2/2010, US patent 7673284, Peng Zhao, KAI-TING WANG, Alexandre Eichenberger, Peng Wu.
  • Method And Apparatus For A Computing System Using Meta Program Presentation, 2/16/2010, US patent 7665070,Krishnan Kailas
  • High Speed Data Channel Including A Cmos Vcsel Driver And A High Performance Photodetector And A Cmos Photoreceiver, 2/9/2010, US patent 7659535, Ferenc Bozso, Philip Emma.
  • Method And System For Dependency Tracking And Flush Recovery For An Out Of Order Microprocessor, 2/9/2010, US patent 7660971, Balaram Sinharoy, Vikas Agarwal, William Burky, Krishnan Kailas.
  • Context Look Ahead Storage Structures, 2/2/2010, US patent 7657726, Thomas Puzak, Philip Emma, Vijayalakshmi Srinivasan, Brian Prasky, Moinuddin Qureshi, Allan Hartstein.
  • Error Correcting Logic System, 1/5/2010, US patent 7642813, Paul Kartschoke, Norman Rohrer, Philip Emma, John Fifield, Kerry Bernstein, Bill Klaasen.