VLIW Architecture - DAISY dynamic translation


The DAISY Concept presents a revolutionary redrawing of the boundaries between hardware and software. DAISY was first unveiled in DAISY: Dynamic Compilation for 100% Architectural Compatibility and presented at ISCA 97.

DAISY addresses both the issues of compatibility with prior architecture generations, such as the IBM PowerPC architecture, IBM System 390, or Intel x86, as well as intergenerational compatibility between generations of VLIW architecture by using established binary distribution formats such as pre-existing architectures, or virtual machines formats such as the Java Virtual Machine.

This approach offers the prospect of combining the high issue rates and a significant advantage in simplicity of VLIW architectures over out-of-order superscalar implementations while addressing key compatibility issues. To attack this compatibility problem, DAISY introduces simple hardware features intended to simplify emulation of existing architectures, so that all existing software for an established architecture (including operating system kernel code) runs without changes.

A detailed description of DAISY can be found at the DAISY website.

The DAISY project resulted in two generations of streamlined high-frequency VLIW architectures, the DAISY tree VLIW architecture, and the BOA bundle-structured VLIW. Both generations benefited from the ability of the software-based DAISY dynamic translator to replace complex source architecture idioms by a sequence of simple streamlined high-performance primitives provided by the target architecture.

Both designs addressed the challenges of providing a high performance execution engine as well as emerging technology issues with an emphasis on streamlined architecture and implementation, as well with breakthrough architecture innovation.

To address the newly emerging challenge posed by wire delay (non-)scaling, the DAISY design included a novel microarchitecture concept of speculatively committing machine state and rolling back in the case of upset events using a set of shadow registers providing a state backup in pipeline registers, as well as associated recovery in architected machine state.

An overview of the DAISY hardware design can be found here. The DAISY architecture and its design are described in An Eight-Issue Tree VLIW Processor for Dynamic Binary Translation presented at ICCD 98.

The DAISY architecture was followed by a second generation of bundle-oriented VLIW architecture known as BOA (Binary translation and Optimization Architecture). Since BOA offered a more narrow issue architecture, it included several architecture aspects to specifically reduce the cost of maintaining the host program state in the dynamic translator, including a group based commit scheme, and a software-controlled checkpoint scheme. To address the increasingly severe issue of wire delay in high-performance microarchitecture, BOA contained a novel stall-free microarchitecture and a high-performance replay mechanism (the recirculation buffer). A description of BOA can be found in Dynamic and Transparent Binary Translation which appeared in IEEE Computer, BOA: Targeting Multi-Gigahertz with Binary Translation which was presented at the 1998 Binary Translation Workshop and received the best paper award, and BOA: The Architecture of a Binary Translation Processor.