Threadmill - DAC2012 Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices


Amir Nahir

Amir Nahir
Manager, Post-Silicon Validation & Design Automation, IBM Research Lab in Haifa.

 


Wisam Kadry

Wisam Kadry
Threadmill Post-Silicon Exerciser Team Lead, Post-Silicon Validation & Design Automation Group, IBM Research Lab in Haifa.

Presentation


Kevin Reick

Kevin Reick
Chief Engineer Power Systems Bring Up, IBM Corp., Austin, TX.

Presentation


Professor Subhasish Mitra

Professor Subhasish Mitra
Departments of Electrical Engineering and Computer Science, Stanford University., Stanford, CA.

Presentation


David S. Erikson

David S. Erikson
Sr. MTS engineer in AMD's Silicon Validation Architecture team, Advanced Micro Devices, Fort Collins, CO.

Presentation


Dr. Brad Quinton

Dr. Brad Quinton
Chief Architect for the Embedded Instrumentation Group at Tektronix, Tektronix, Inc., Vancouver, BC, Canada.

Presentation


Professor Alan J. Hu

Professor Alan J. Hu
Department of Computer Science University of British Columbia, Vancouver, BC, Canada.

Presentation


Keshavan Tiruvallur

Keshavan Tiruvallur
Intel Fellow in the Intel Architecture Group, Platform Validation Engineering, Intel Corp., Portland, OR.

Presentation


Nagib Hakim

Nagib Hakim
Principal Engineer in the Platform Validation Engineering dep, Intel Corp., Santa Clara, CA.

Presentation


Professor Valeria Bertacco

Professor Valeria Bertacco
Department of Electrical Engineering and Computer Science. University of Michigan, Ann Arbor, MI.

Presentation


Sharad Kumar

Sharad Kumar
Manager, SoC post silicon validation and emulation, Freescale Semiconductor, Inc., Noida, India.

Presentation


Harry Foster

Harry Foster
Chief Scientist for Verification, Mentor Graphics Corp., Plano, TX.

Presentation