Atomic Layer Etching       


Robert L. Bruce photo photoERIC A. JOSEPH photo Nathan Marchack photo Hiroyuki  (Hiro) Miyazoe photo photo Hongwen  (Wendy) Yan photo

Atomic Layer Etching - ALEt

 Feasibility for atomic layer etching (ALE) has been proposed and demonstrated on a lab scale for some time. Dating back to the early 1990s, researchers first recognized the ability to control etch processes down to the atomic scale for III-V materials. Meguro et al[3] used alternating cycles of a pulsed chemical etchant (Cl2) and an energetic electron beam to demonstrate ‘digital etching’ of GaAs substrates. With this approach, self-limiting etch rates of as little as ~1 Å/cycle (equivalent to 1/3 of a monolayer per cycle) were reported.3 In a different approach (derived from molecular beam epitaxy), Tsang et al. also showed sub-monolayer precision GaAs removal by injecting AsCl3 directly onto a heated sample surface in a chemical beam epitaxy chamber.[4] This approach demonstrated not only the ability to control a flux driven process down to the Angstrom level, but also the ability to modify interface properties and/or change surface morphology. For Si-based etch systems, Matsuura demonstrated feasibility for ALE using a 4-step process including alternating cycles of chlorine (gas only), followed by exposure to an Ar+ ion beam with an ion energy chosen to ensure self-limiting mono-layer removal.[5] Similarly, Sakaue et al. also demonstrated ALE capability for silicon, however their approach utilized alternating cycles of a fluorine containing downstream plasma (CF4/O2, NF3/N2 or F2/He) at cryogenically cooled substrate temperatures followed by Ar+ ion irradiation.[6]

 ALE schematic

While each of these approaches demonstrates merit and significance for atomic layer etching, the adoption of ALE had not garnered significant interest until now. In the recent past, the focus of plasma etch equipment has been on the ability to minimize damage and/or increase etch pattern fidelity by means of either tailoring ion energy distributions or reducing the average electron temperature of the plasma. For example, early work by Sobolewski[7] and Wendt[8] demonstrated the ability to modify ion energy distribution functions via plasma frequency or pulsed DC bias modulation to enable ion extraction with either narrow or broad energy distributions. This work was further expanded upon with the exploration of multi-frequency drive electrodes[9],[10], the inclusion of DC superposition [DCS][11],[12] and/or more elaborate plasma pulsing combinations of both source and/or bias powers to reduce ion energy and/or enable charge balance.[13],[14],[15] Novel plasma sources which produce a more self-confined, high density plasma with significantly reduced electron temperature at the wafer surface have also been evaluated.[16],[17],[18] Furthermore, these recent concepts have been successfully commercialized and shown to reduce plasma damage and/or improve pattern fidelity.[19],[20],[21],[22]


Ironically, it is these same hardware enhancements that have set the stage to enable processing capability for atomic scale precision. Plasma pulsing,low electron temperature plasmas, pulsed gas flows etc., which are now incorporated into state of the art plasma processing toolsets are envisioned to be key advances to potentially enable ALE in a large scale production setting. However, a unified methodology and/or system to achieve high volume manufacturing with atomic scale precision has yet to be defined and/or developed for a variety of Si-based material systems (Si, SiO2, Si3N4, SiCOH).  


 Much of the most recent ALE activity was focussed on Si ALE using Cl2 adsoprtion. One review on this can be found in [23]


[3] T. Meguro, M. Hamagaki et al., “Digital etching of GaAs: New approach of dry etching to atomic ordered processing”, Appl. Phys. Lett. 56(16), 1552-1554 (1990)

[4] W.T. Tsang, T.H. Chiu and R.M. Kapre, “Monolayer chemical beam etching: Reverse molecular beam epitaxy”, Appl. Phys. Lett. 63, 3500-3502 (1993)

[5] T. Matsuura, J. Murota et al., “Self-limited layer-by-layer etching of Si by alternated chlorine adsorption and Ar+ ion irradiation”, Appl. Phys. Lett. 63(20), 2803-2805 (1993)

[6] H. Sakaue, S. Iseda et al., “Atomic Layer Controlled Digital Etching of Silicon”, Jpn. J. Appl. Phys. 29(11), 2648-3652 (1990)

[7] M. Sobolewski, Y. Wang and A. Goyette, “Measurements and modeling of ion energy distributions in high-density, radio-frequency biased CF4 discharges”, J. Appl. Phys. 91(10), 6303-6314 (2002)

[8] S.-B. Wang and A. E. Wendt, “Control of ion energy distribution at substrates during plasma processing”, Journal of Applied Physics 88 (2), 643-646 (2000)

[9] X.S. Li, Z.H. Bi et al., “Modulating effects of the low-frequency source on ion energy distributions in a dial frequency capacitively coupled plasma”, Appl. Phys. Lett. 93, 031504 (2008)

[10] H.C. Kim and J.K. Lee, “Dual radio-frequency discharges: Effective frequency concept and effective frequency transition”, J. Vac. Sci. Technol. A 23(4), 651-657 (2005)

[11] T. Yamaguchi, T. Komuro et al., “Direct current superposed dual-frequency capacitively coupled plasmas in selective etching of SiCOH over SiC”, J. Phys. D: Appl. Phys. 45, 025203 (2012)

[12] M. Honda and K. Yatsuda, “Patterning Enhancement Techniques by Reactive Ion Etch”, Proc. SPIE 8328, 832809 (2012)

[13] O. Joubert, M. Darnon et al., “Towards new plasma technologies for 22nm gate etch processes and beyond”, Proc. SPIE 8328, 83280D (2012)

[14] S. Banna, A. Agarwal et al., “Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching”, IEEE Transactions on Plasma Science 37 (9), 1730-1746 (2009)

[15] S. Banna, A. Agarwal et al., “Pulsed high-density plasmas for advanced dry etching processes”, J. Vac. Sci. Technol. A 30(4), 040801 (2012)

[16] L. Chen and Q. Yang, “Properties of RLSA microwave surface wave plasma and its applications to finFET fabrication”, Proc. SPIE 8685, 86850H (2013)

[17]S.G. Walton, E.H. Lock and R.F.Fernsler, “Plasma modification of solid and porous polyethylene”, Plasma Proc. And Poly. 5, 453-459 (2008)

[18] E.H. Lock, R.F. Fernsler et al., MRL Memo Report (2011)

[19] M. Darnon, M. Haass et al., “Characterization of silicon etching in synchronized pulsed plasma”, Proc. SPIE 8685, 86850J (2013)

[20] T. Goto, H. Yamauchi et al., “High-Speed Damage-Free Contact Hole Etching Using Dual Shower Head Microwave-Excited High-Density-Plasma Equipment”, Jpn. J. Appl. Phys. 43, 1784 (2004)

[21] D.H. Choi, D.G. Yang et al., “Tall FIN formation for FINFET devices of 20nm and beyond using multi-cycles of passivation and etch processes”, Proc. SPIE 8685, 86850D (2013)

[22] M.K. Ahn, W.J. Kwon et al., “Etch challenges for 1xnm NAND flash”, Proc. SPIE 8328, 83280F (2012)

[23] K.J. Kanarik, T. Lill et al., "Overview of Atomic Layer etching in the semiconductor industry", J. Vac. Sci. Technol. A 33, 020802 (2015);