Storage Class Memory at Almaden       

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 Noel Arellano photo Donald S. Bethune photoGeoffrey W. Burr photoERIC A. JOSEPH photo Hiroyuki  (Hiro) Miyazoe photoStuart S.P. Parkin photoCharles T. Rettner photo Kevin P. Roche photoLeslie E. Thompson photoKUMAR VIRWANI photo

Storage Class Memory at Almaden - MIEC Novel Diode


The MIEC novel diode is a BEOL-friendly access device (AD) based on Cu-containing MIEC materials which exhibits large voltage margin Vm, ultra-low leakage (<10pA), and high endurance (>1e8) at high current densities. As a high-performance, non-silicon device offering >7 orders of magnitude ON-OFF ratio for both positive and negative applied biases, the MIEC-based AD is ideal for enabling high-density stacking of 3-D crosspoint memory in the BEOL for nearly any non-volatile memory device.

Using a CMOS-compatible diode-in-via (DIV) process and in-house CMP process, MIEC ADs have been integrated in arrays up to 512x1024 in size at 100% yield.

Numerous desirable attributes have been demonstrated: the large currents (>200uA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage (< 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays. MIEC ADs also support a broad and flexible processing window, and can survive temperatures up to 500degC.

MIEC ADs have been shown to scale to the <30nm CDs and <12nm thicknesses found in advanced technology nodes. Switching speeds at the high (>100uA) currents of NVM writes can reach 15ns; NVM reads at typical (<5uA) current levels can be <<1usec.

Journal publications

  1. "Exploring the design space for crossbar arrays built with Mixed-Ionic-Electronic-Conduction (MIEC) access devices," P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. N. Kurdi, and K. Gopalakrishnan, IEEE Journal of the Electron Devices Society, 3(5) 423--434 (2015).

     

  2. "On the origin of steep I-V nonlinearity in Mixed-Ionic-Electronic-Conduction (MIEC)-based Access Devices," A. Padilla, G. W. Burr, R. S. Shenoy, K. V. Raman, D. S. Bethune, R. M. Shelby, C. T. Rettner, J. Mohammad, K. Virwani, P. Narayanan, A. K. Deb, R. K. Pandey, M. Bajaj, K. V. R. M. Murali, B. N. Kurdi, and K. Gopalakrishnan, IEEE Transactions on Electron Devices, 62(3), 963--971 (2015).

     

  3. "Invited Review: MIEC (Mixed-Ionic-Electronic-Conduction)-based access devices for non-volatile crossbar memory arrays," R. S. Shenoy, G. W. Burr, K. Virwani, B. Jackson, A. Padilla, P. Narayanan, C. T. Rettner, R. M. Shelby, D. S. Bethune, K. V. Raman, M. Brightsky, E. Joseph, P. M. Rice, T. Topuria, A. J. Kellock, B. Kurdi, and K. Gopalakrishnan, Semiconductor Science and Technology, 29(10), 104005 (2014).

     

  4. "Access devices for 3-D crosspoint memory," G. W. Burr, R. S. Shenoy, P. Narayanan, K. Virwani, A. Padilla B. Kurdi, and H. Hwang, Journal of Vacuum Science & Technology B, 32(4), 040802 (2014).

     

 

Major Conference Publications

  1. "Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays," P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. Kurdi, 2014 IEEE International Electron Devices Meeting (IEDM 2014), 29.7, December 2014.

     

  2. "Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D Crosspoint Memory based on Mixed-Ionic-Electronic-Conduction (MIEC)," G. W. Burr, K. Virwani, R. S. Shenoy, G. Fraczak, C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, 2013 Symposium on VLSI Technology, T6.4, June 2013.

     

  3. "Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials," K. Virwani, G. W. Burr, R. S. Shenoy, C. T. Rettner, A. Padilla, T. Topuria, P. M. Rice, G. Ho, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, 2012 IEEE International Electron Devices Meeting (IEDM 2012), December 2012.

     

  4. "Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield," G. W. Burr, K. Virwani, R. S. Shenoy, A. Padilla, M. BrightSky, E. A. Joseph, M. Lofaro, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice, B. N. Kurdi, and K. Gopalakrishnan, 2012 Symposium on VLSI Technology, T5-4, June 2012.

     

  5. "Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials," R. S. Shenoy, K. Gopalakrishnan, B. Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, D. S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, 2011 Symposium on VLSI Technology, T5B-1, June 2011.

     

  6. "Highly-Scalable Novel Access Device based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays," K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, D. S. Bethune, R. M. Shelby, G. W. Burr, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, 2010 Symposium on VLSI Technology, 19.4, June 2010.

 

Overview Presentations

  1. "MIEC-based Access Devices for 3D-Crosspoint Nonvolatile Memory Arrays"
  2. "SCMandMIEC_overview_12Feb2013 "

 

Applications of MIEC

 

  1. "Optimization of Conductance Change in {Pr$_{1-x}$Ca$_x$MnO$_3$-based} Synaptic Devices for Neuromorphic Systems," J.-W. Jang, S. Park, G. W. Burr, H. Hwang, and Y.-H. Jeong, IEEE Electron Device Letters, 36(5), 457-459 (2015).

     

  2. "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," G. W. Burr, R. M. Shelby, C. di Nolfo, J. W. Jang, R. S. Shenoy, P. Narayanan, K. Virwani, E. U. Giacometti, B. Kurdi, and H. Hwang, 2014 IEEE International Electron Devices Meeting (IEDM 2014), 29.5, December 2014.

     

  3. "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," G. W. Burr, R. M. Shelby, C. di Nolfo, J. W. Jang, I. Boybat, R. S. Shenoy, P. Narayanan, K. Virwani, E. U. Giacometti, B. Kurdi, and H. Hwang, IEEE Transactions on Electron Devices, special issue commemorating the 60th anniversary of IEDM, 62(11), 3498--3507 (2015).

     

  4. "Large-scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power)," G. W. Burr, P.Narayanan, R.M.Shelby, S. Sidler, I.Boybat, C.di Nolfo, and Y.Leblebici, 2015 IEEE International Electron Devices Meeting (IEDM 2015), invited talk, 4.4, December 2015.

     

 

Other publications

  1. "Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed-Ionic-Electronic-Conduction (MIEC)-based access devices," P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. Kurdi, and K. Gopalakrishnan, Device Research Conference, paper V.-A5, June 2014.

     

  2. "The origin of massive nonlinearity in mixed-Ionic-Electronic-Conduction (MIEC)-based access devices, as revealed by numerical device simulation," A. Padilla, G. W. Burr, R. S. Shenoy, K. V. Raman, D. Bethune, R. M. Shelby, C. T. Rettner, J. Mohammad, K. Virwani, P. Narayanan, A. K. Deb, R. K. Pandey, M. Bajaj, K. V. R. M. Murali, B. N. Kurdi, and K. Gopalakrishnan, Device Research Conference, poster III-53, June 2014.

     

 

Patents

  1. "Rectifying element for a crosspoint based memory array architecture," K. Gopalakrishnan, US 7,382,647, granted June 3, 2008.

     

  2. "Electrolytic device based on a solution-processed electrolyte," K. Gopalakrishnan, D. B. Mitzi, and R. S. Shenoy, US 7,928,419, granted April 19, 2011.

     

  3. "Use of a symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory," K. Gopalakrishnan, US 7,929,335, granted April 19, 2011.

     

  4. "Backend of Line (BEOL) compatible high current density access device for high density arrays of electronic components," D. S. Bethune, K. Gopalakrishnan, A. J. Kellock, and R. S. Shenoy, US 2011/0227023, filed March 19, 2010.

     

  5. "Low temperature BEOL-compatible diode having high voltage margins for use in large arrays of electronic components," D. S. Bethune, K. Gopalakrishnan, A. Kellock, R. Shenoy, and K. Virwani, filed August 2011.

     

  6. "Non-volatile memory crosspoint repair," G. W. Burr, ARC920120022US1/ARC1P013, filed June 2012.