Project Name
Reliability-Aware Microarchitectures
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2011
Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system
M K Gschwind, R A Philhower, R C Yeung
US Patent 7,925,853
2009
Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system
P Bose, A Buyuktosunoglu, C Y Cher, M K Gschwind, R Nair, R A Philhower, W Sauer, R C Yeung
US Patent 7,627,742
TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT
Eren Kursun, Philip G. Emma, Jude A Rivers
US Patent App. 12/493,599
System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems
P Bose, J A Rivers, J Srinivasan
US Patent 7,506,216
Reliability challenges and system performance at the architecture level
J A Rivers, P Kudva
Design \& Test of Computers, IEEE 26(6), 62--73, IEEE, 2009
2008
SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP
Eren Kursun, J udeA Rivers, Pradip Bose, Victor Zyuban
US Patent App. 12/174,198
Lifetime Reliability Awareness for Microprocessors
J Srinivasan, S V Adve, P Bose, J A Rivers
2008 - Citeseer, Citeseer
PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES
P Bose, Z Hu, J A Rivers, J Shin, V Zyuban
US Patent App. 12/189,416
Modeling System-Level Effects of Soft Errors
P Bose, P N Kudva, J A Rivers, P N Sanda, J Wellman
US Patent App. 20,100/083,203
Phaser: Phased methodology for modeling the system-level effects of soft errors
JA Rivers, P Bose, P Kudva, J D Wellman, PN Sanda, EH Cannon, LC Alves
IBM Journal of Research and Development 52(3), 293--306, IBM, 2008
2007
METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME
P Bose, Z Hu, J A Rivers, J Shin, V Zyuban
US Patent App. 20,080/256,383
RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM
P Bose, P G Emma, J A Rivers, S W Sathaye
US Patent App. 11/684,987
2005
Exploiting structural duplication for lifetime reliability enhancement
J Srinivasan, S V Adve, P Bose, J A Rivers
ACM SIGARCH Computer Architecture News 33(2), 520--531, ACM, 2005
Lifetime reliability: Toward an architectural solution
J Srinivasan, S V Adve, P Bose, J A Rivers
IEEE Micro 25(3), 70--80, 2005
2004
The case for microarchitectural awareness of lifetime reliability
J Srinivasan, S V Adve, P Bose, J A Rivers
Proc, 2004
The case for lifetime reliability-aware microprocessors
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society
The Impact of Technology Scaling on Lifetime Reliability (PDF)
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society
2003
Ramp: A model for reliability aware microprocessor design
J Srinivasan, S V Adve, P Bose, J Rivers, C K Hu
IBM Research Report, Citeseer, 2003
2000
Performance and functional verification of microprocessors
P Bose, J A Abraham
VLSI Design, 2000, pp. 58--63
1999
Validation of Turandot, a processor model for microarchitecture exploration
Pradip Bose, Jaime H Moreno, M. Moudgill
IBM Research Report RC21378, 1999
Validation of Turandot, a fast processor model for microarchitecture exploration
M Moudgill, P Bose, J H Moreno
Performance, Computing and Communications Conference, 1999, pp. 451--457
Challenges in processor modeling and validation
P Bose, T M Conte, T M Austin
IEEE Micro 19(3), 9--14, 1999
1998
Others
The Case for Lifetime Reliability-Aware Microprocessors Ѓ
J Srinivasan, S V Adve, P Bose, J A Rivers
ece.northwestern.edu, 0
Balancing new reliability challenges and system performance at\&\# xD; the architecture level
P Kudva, J Rivers
Design \& Test of Computers, IEEE pp. 99, 1, IEEE, 0