Prashant Nair  Prashant  Nair photo       

contact information

Post Doctoral Researcher
Thomas J. Watson Research Center, Yorktown Heights, NY USA

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Professional Associations

Professional Associations:  ACM SIGARCH  |  IEEE Computer Society


2017

DICE: Compressing DRAM Caches for Bandwidth and Capacity
Young, Vinson and Nair, Prashant J and Qureshi, Moinuddin K
Proceedings of the 44th Annual International Symposium on Computer Architecture, pp. 627--638, 2017
Abstract

Architectural Techniques to Enable Reliable and Scalable Memory Systems
Nair, Prashant J
arXiv preprint arXiv:1704.03991, 2017
Abstract


2016

XED: exposing on-die error detection information for strong memory reliability
Nair, Prashant J and Sridharan, Vilas and Qureshi, Moinuddin K
Computer Architecture (ISCA), 2016 ACM/IEEE 43rd Annual International Symposium on, pp. 341--353
Abstract

Citadel: Efficiently protecting stacked memory from TSV and large granularity failures
Nair, Prashant J and Roberts, David A and Qureshi, Moinuddin K
ACM Transactions on Architecture and Code Optimization (TACO) 12(4), 49, ACM, 2016
Abstract

Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
Chang, Kevin K and Nair, Prashant J and Lee, Donghyuk and Ghose, Saugata and Qureshi, Moinuddin K and Mutlu, Onur
High Performance Computer Architecture (HPCA), 2016 IEEE International Symposium on, pp. 568--580
Abstract

F ault S im: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems
Nair, Prashant J and Roberts, David A and Qureshi, Moinuddin K
ACM Transactions on Architecture and Code Optimization (TACO) 12(4), 44, ACM, 2016
Abstract


2015

Reducing read latency of phase change memory via early read and turbo read
Nair, Prashant J and Chou, Chiachen and Rajendran, Bipin and Qureshi, Moinuddin K
High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on, pp. 309--319
Abstract

DEUCE: Write-efficient encryption for non-volatile memories
Young, Vinson and Nair, Prashant J and Qureshi, Moinuddin K
ACM SIGARCH Computer Architecture News, pp. 33--44, 2015
Abstract

Architectural support for mitigating row hammering in DRAM memories
Kim, Dae-Hyun and Nair, Prashant J and Qureshi, Moinuddin K
IEEE Computer Architecture Letters 14(1), 9--12, IEEE, 2015
Abstract

AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
Qureshi, Moinuddin K and Kim, Dae-Hyun and Khan, Samira and Nair, Prashant J and Mutlu, Onur
Dependable Systems and Networks (DSN), 2015 45th Annual IEEE/IFIP International Conference on, pp. 427--437
Abstract

Reducing refresh power in mobile devices with morphable ECC
Chou, Chiachen and Nair, Prashant and Qureshi, Moinuddin K
Dependable Systems and Networks (DSN), 2015 45th Annual IEEE/IFIP International Conference on, pp. 355--366
Abstract


2014

Refresh pausing in DRAM memory systems
Nair, Prashant J and Chou, Chia-Chen and Qureshi, Moinuddin K
ACM Transactions on Architecture and Code Optimization (TACO) 11(1), 10, ACM, 2014
Abstract

FAULTSIM: A fast, configurable memory-resilience simulator
Roberts, D and Nair, P
The Memory Forum: In conjunction with ISCA, 2014
Abstract


2013

A case for refresh pausing in DRAM memory systems
Nair, Prashant and Chou, Chia-Chen and Qureshi, Moinuddin K
High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, pp. 627--638
Abstract

ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
Nair, Prashant J and Kim, Dae-Hyun and Qureshi, Moinuddin K
ACM SIGARCH Computer Architecture News, pp. 72--83, 2013
Abstract

Designing low power SRAM system using energy compression
Nair, Prashant
Master's Thesis, 2013
Abstract