Cindy Eisner  Cindy Eisner photo       

contact information

Senior Technical Staff Member
Haifa Research Lab, Haifa, Israel



Relative equivalence in the presence of ambiguity
Oshri Adler, Cindy Eisner, Tatyana Veksler
Computer Aided Verification, pp. 430--446, 2013


Resurrecting infeasible clock-gating functions
Eli Arbel, Cindy Eisner, Oleg Rokhlenko
DAC '09: Proceedings of the 46th Annual Design Automation Conference, pp. 160--165, ACM, 2009

Structural contradictions
C Eisner, D Fisman
Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing, pp. 164--178, Springer, 2009

Functional verification of power gated designs by compositional reasoning
Cindy Eisner, Amir Nahir, Karen Yorav
Computer Aided Verification: 20th International Conference, CAV 2008 Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 40-55, Springer, 2009


Session 12: Hardware Verification I-Functional Verification of Power Gated Designs by Compositional Reasoning
C Eisner, A Nahir, K Yorav
Lecture Notes in Computer Science5123, 433--445, Berlin: Springer-Verlag, 1973-, 2008

Proposed New Appendix B for IEEE 1850 (PSL)
C Eisner, D Fisman
2008 -, Technical Report H-0257, IBM, 2008

Augmenting a regular expression-based temporal logic with local variables
C Eisner, D Fisman
Formal Methods in Computer-Aided Design, 2008, pp. 1--8

Policy Validation for System Automation: A Case Study
E Zarpas, C Eisner, S Tal
Policies for Distributed Systems and Networks, 2008, pp. 46--53


PSL for Runtime Verification: Theory and Practice. Runtime Verification, LNCS 4839
C Eisner
2007 - Springer, Springer

ExpliSat: Guiding SAT-based software verification with explicit states
S Barner, C Eisner, Z Glazberg, D Kroening, I Rabinovitz
Hardware and Software, Verification and Testing4383, 138--154, Springer, 2007


The,⊥ approach for truncated semantics
C Eisner, D Fisman, J Havlicek, J M{aa}rtensson
Technical Report, 2006

A practical introduction to PSL
C Eisner, D Fisman
2006 -, Springer-Verlag New York Inc


Formal verification of software source code through semi-automatic modeling
C Eisner
Software and Systems Modeling 4(1), 14--31, Springer, 2005

A topological characterization of weakness
Cindy Eisner, Dana Fisman, John Havlicek
Proceedings of the twenty-fourth annual ACM symposium on Principles of distributed computing, pp. 1--8, ACM, 2005



The definition of a temporal clock operator
C Eisner, D Fisman, J Havlicek, A McIsaac, D Van Campenhout
Automata, Languages and Programming, 193--193, Springer, 2003

Reasoning with temporal logic on truncated paths
C Eisner, D Fisman, J Havlicek, Y Lustig, A McIsaac, D Van Campenhout
Computer Aided Verification, pp. 27--39, Springer, 2003

Model Checking at IBM
S Ben-David, C Eisner, D Geist and Y Wolfsthal
Formal Methods in System Design 22(2), 101--108, Springer, 2003


Sugar 2.0 proposal presented to the accellera formal verification technical committee
C Eisner, D Fisman
i> http://www. haifa. il. ibm. com/projects/verification/sugar/Sugar\_2. 0\_Accellera. ps, Citeseer, 2002

Using symbolic CTL model checking to verify the railway stations of Hoorn-Kersenboogerd and Heerhugowaard
C Eisner
International Journal on Software Tools for Technology Transfer (STTT) 4(1), 107--124, Springer, 2002

Comparing symbolic and explicit model checking of a software system
C Eisner, D Peled
Model Checking Software, 79--82, Springer, 2002

Establishing PCI compliance using formal verification: a case study
I Beer, S Ben-David, C Eisner, Y Engel, R Gewirtzman, A Landver
Computers and Communications, 1995, pp. 373--377, 2002


Model checking the garbage collection mechanism of SMV
C Eisner
Electronic Notes in Theoretical Computer Science 55(3), 289--303, Elsevier, 2001

On the Effective Deployment of Functional Formal Verification
Y Abarbanel-Vinov, N Aizenbud-Reshef, I Beer, C Eisner, D Geist, T Heyman, I Reuveni, E Rippel, I Shitsevalov and Y Wolfsthal
Formal Methods in System Design 19(1), 35--44, Springer, 2001

Efficient detection of vacuity in temporal model checking
I Beer, S Ben-David, C Eisner, Y Rodeh
Formal Methods in System Design 18(2), 141--163, Springer, 2001

The temporal logic Sugar
I Beer, S Ben-David, C Eisner, D Fisman, A Gringauze, Y Rodeh
Computer Aided Verification, pp. 363--367, Springer, 2001


A methodology for formal design of hardware control with application to cache coherence protocols
Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne Nation, Kyle Nelson, Ken Valk
Proceedings of the 37th Annual Design Automation Conference, pp. 724--729, ACM, 2000



Efficient detection of vacuity in ACTL formulas
I Beer, S Ben-David, C Eisner, Y Rodeh
Computer Aided Verification, pp. 279--290, Springer, 1997

RuleBase: Model Checking at IBM
I Beer, S Ben-David, C Eisner, D Geist, L Gluhovsky, T Heyman, A Landver, P Paanah, Y Rodeh, G Ronin and Y Wolfsthal
Computer Aided Verification (CAV '97), pp. 480--483, Springer, 1997


RuleBase: an industry-oriented formal verification tool
Ilan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver
Proceedings of the 33rd annual Design Automation Conference, pp. 655--660, ACM, 1996

Year Unknown

Formal syntax and Semantics of PSL: Appendix B of Accellera’s Property Specification Language Reference Manual
D Fisman, C Eisner, J Havlicek
Accellera (March 2004)