Rahul M Rao  Rahul M Rao photo       

contact information

Senior Technical Staff Memer, Enterprise Systems Development
Bangalore, India
  +91dash80dash406dash61261

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Professional Associations

Professional Associations:  ACM  |  IEEE Member


2015

Virtual logic netlist: Enabling efficient RTL analysis
Spandana Rachamalla, Arun Joseph, Rahul Rao, Diwesh Pandey
Quality Electronic Design (ISQED), 2015 16th International Symposium on, pp. 571--576

IBM POWER8 circuit design and energy optimization
V Zyuban, J Friedrich, DM Dreps, J Pille, DW Plass, PJ Restle, ZT Deniz, MM Ziegler, S Chu, Shariful Islam, others
IBM Journal of Research and Development 59(1), 9--1, IBM, 2015


2014

Introduction to special issue on reliability and device degradation in emerging technologies
Rahul Rao, Fadi Gebara
ACM Journal on Emerging Technologies in Computing Systems (JETC) 10(1), 1, ACM, 2014


2013

Design of Deep Sub-Micron CMOS Circuits and Design Methodologies for High Performance Microprocessor
Ruchir Puri, Charudhattan Nagarajan, Sourav Saha, IBM Sridhar Rangarajan, Rahul Rao, Puneet Gupta
Tutorial, VLSI Design, 2013. Proceedings. 26th International Conference on,

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
Amlan Ghosh, Rahul M Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B Brown
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 21(9), 1683--1692, IEEE, 2013

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis
Nagu Dhanwada, David Hathaway, Victor Zyuban, Peng Peng, Karl Moody, William Dungan, Arun Joseph, Rahul Rao, Christopher Gonzalez
Proceedings of the International Conference on Computer-Aided Design, pp. 458--465, 2013

IBM POWER7+ design for higher frequency at fixed power
V Zyuban, SA Taylor, Bjoern Christensen, AR Hall, CJ Gonzalez, J Friedrich, F Clougherty, J Tetzloff, Ramesh Rao
IBM Journal of Research and Development 57(6), 1--1, IBM, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator
Yuji Higuchi, Ken-ichi Shinkai, Mime Hashimoto, Rahul Rao, Sani Nassif
Test Symposium (ETS), 2013 18th IEEE European, pp. 1--6


2012

Usage-based degradation of SRAM arrays due to bias temperature instability
Bansal, Aditya and Kim, Jae-Joon and Rao, Rahul
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 2F--6
Abstract

Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache
Subho Chatterjee, Minki Cho, Rahul Rao, Saibal Mukhopadhyay
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2012 28th Annual IEEE, pp. 14--19


2011

Forecasting BTI Impact in Circuits : It is Sunny and Humid with chances of Rain
A. Bansal, J. Kim, R. Rao
Tutorial at Reliability Physics Symposium (IRPS), 2011 IEEE International, IEEE

Bias Temperature Instability model for digital circuits-predicting instantaneous FET response
Aditya Bansal, Kai Zhao, Jae-Joon Kim, Rahul Rao
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. CR--2

Separating NBTI and PBTI effects on the Degradation of Ring Oscillator Frequency
Barry P Linder, Jae-Joon Kim, Rahul Rao, Keith Jenkins, Aditya Bansal
Integrated Reliability Workshop Final Report (IRW), 2011 IEEE International, pp. 1--6

PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability
Jae-Joon Kim, Rahul M Rao, Jeremy Schaub, Amlan Ghosh, Aditya Bansal, Kai Zhao, Barry P Linder, James Stathis
VLSI Circuits (VLSIC), 2011 Symposium on, pp. 224--225

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS
DP Ioannou, K Zhao, A Bansal, B Linder, R Bolam, E Cartier, J-J Kim, R Rao, G La Rosa, G Massey, others
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. CR--1

Reliability monitoring ring oscillator structures for isolated/combined NBTI and PBTI measurement in high-k metal gate technologies
Jae-Joon Kim, Barry P Linder, Rahul M Rao, Tae-Hyoung Kim, Pong-Fei Lu, Keith Jenkins, Chris H Kim, Aditya Bansal, Saibal Mukhopadhyay, Ching-Te Chuang, others
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. 2B--4

Power optimization methodology for the IBM POWER7 microprocessor
V Zyuban, J Friedrich, CJ Gonzalez, R Rao, MD Brown, MM Ziegler, H Jacobson, S Islam, S Chu, P Kartschoke, others
IBM Journal of Research and Development 55(3), 7--1, IBM, 2011

SRAM write-ability improvement with transient negative bit-line voltage
Saibal Mukhopadhyay, Rahul M Rao, Jae-Joon Kim, Ching-Te Chuang
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19(1), 24--32, IEEE, 2011


2010

High Performance Design and Methodology in a 3D Integration Process
Ivan Vo, Tuyet Nguyen, Fadi Gebara, Jeremy Schaub, Rahul Rao, Jente B Kuang, Gary Carpenter, Kevin Nowka
Solid State Symposium - VLSI & Related Technologies, Vietnam, 2010

Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair
Swarup Bhunia, Rahul Rao
IEEE Design \& Test of Computers pp. 6, 4--5, IEEE, 2010

Variations: sources and characterization
Aditya Bansal, Rahul M Rao
Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3--39, Springer, 2010

Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
Harmander Singh, Rahul Rao, Kanak Agarwal, Dennis Sylvester, Richard Brown
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18(1), 166--170, IEEE, 2010

Parameter Variations and Low-Power Design: Test Issues and On-Chip Calibration/Repair Solutions
R. Rao, S. Mukhopadhayay, S. Bhunia, P. Elakkumanan
VLSI Test Symposium (VTS), IEEE, 2010

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement
J J Kim, R Rao, K Kim
Custom Integrated Circuits Conference (CICC), 2010 IEEE, IEEE


2009

On-chip negative bias temperature instability sensor using slew rate monitoring circuitry
Amlan Ghosh, Rahul M Rao, Richard B Brown, Ching-Te Chuang
ACM IEEE Intl. Symposium on Low Power Electronics and Design, Citeseer, 2009

A precise negative bias temperature instability sensor using slew-rate monitor circuitry
Amlan Ghosh, Richard B Brown, Rahul M Rao, Ching-Te Chuang
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 381--384

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
Amlan Ghosh, Rahul M Rao, Richard B Brown
Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, pp. 45--50

A local random variability detector with complete digital on-chip measurement circuitry
Rahul Rao, Keith Jenkins, Jae-Joon Kim, others
Solid-State Circuits, IEEE Journal of 44(9), 2616--2623, IEEE, 2009

Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors
Jae-Joon Kim, Aditya Bansal, Rahul Rao, Shih-Hsien Lo, Ching-Te Chuang
Electron Device Letters, IEEE 30(8), 852--854, IEEE, 2009

Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance
Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H Stathis, Ching-Te Chuang
Reliability Physics Symposium, 2009 IEEE International, pp. 745--749

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H Stathis, Ching-Te Chuang
Microelectronics reliability 49(6), 642--649, Elsevier, 2009

Parameter Variations and Self-Calibration / Self-Repair Solutions in Nanometer Technologies
S. Mukhopadhyay, R. Rao, P. Elakkumanan, S. Bhunia
Tutorial at International Test Conference, 2009, IEEE


2008

Variability and power management in sub-100nm SOI technology for reliable high performance systems
Koushik Das, Kerry Bernstein, Jeff Burns, Fadi Gebara, Shih-Hsien Lo, Kevin Nowka, Rahul Rao, Michael Rosenfield
SOI Conference, 2008. SOI. IEEE International, pp. 1--4

Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects
Jae-Joon Kim, Rahul Rao, Saibal Mukhopadhyay, Ching-Te Chuang
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pp. 163--166

On-chip process variation detection and compensation using delay and slew-rate monitoring circuits
Amlan Ghosh, Rahul M Rao, Ching-Te Chuang, Richard B Brown
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, pp. 815--820

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies
Saibal Mukhopadhyay, R Rao, Jae-Joon Kim, Ching-Te Chuang
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pp. 384--387

A completely digital on-chip circuit for local-random-variability measurement
Rahul Rao, Keith Jenkins, Jae-Joon Kim, others
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 412--623

On-chip process variation detection using slew-rate monitoring circuit
Amlan Ghosh, Rahul M Rao, Jae-joon Kim, Ching-Te Chuang, Richard B Brown
VLSI Design, 2008. VLSID 2008. 21st International Conference on, pp. 143--149


2007


Dual Issue Power PC FXU
Jayakumaran Sivagnaname, Rahul Rao, Richard B Brown
Technical Report, Citeseer, 2007

On-chip Process Variation Detection and Compensation for Parametric Yield Enhancement in sub-100nm CMOS technology
Amlan Ghosh, Rahul M Rao, Richard B Brown, Ching-Te Chuang
Austin Center for Advanced Studies Workshop, Citeseer, 2007

Accurate modeling and analysis of currents in trapezoidal FinFET devices
R Rao, A Bansal, J Kim, K Roy, CT Chuang
2007 IEEE International SOI Conference

Parametric yield analysis and optimization in leakage dominated technologies
Kanak Agarwal, Rahul Rao, Dennis Sylvester, Richard Brown
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15(6), 613--623, IEEE, 2007

High-performance SRAM in nanoscale CMOS: Design challenges and techniques
Ching-Te Chuang, Saibal Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, Rahul Rao
Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on, pp. 4--12


2005

Power-aware global signaling strategies
Dennis Sylvester, Himanshu Kaul, Kanak Agarwal, Rahul M Rao, Sani Nassif, Richard B Brown
IEEE International Symposium on Circuits and Systems1, 604, IEEE; 1999, 2005

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength
Harmander Singh Deogun, Dennis Sylvester, Rahul Rao, Kevin Nowka
SOC Conference, 2005. Proceedings. IEEE International, pp. 147--150

Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization
Harmander Singh Deogun, Rahul Rao, Dennis Sylvester, Richard Brown, Kevin Nowka
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, pp. 88--93

Parametric yield analysis and constrained-based supply voltage optimization
Rahul Rao, Kanak Agarwal, Anirudh Devgan, Kevin Nowka, Dennis Sylvester, Richard Brown
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, pp. 284--290

Silicon-on-insulator MOSFETs with hybrid crystal orientations
M Yang, K Chan, A Kumar, S H Lo, J Sleight, L Chang, R Rao, S Bedell, A Ray, J Ott, others
VLSI Technology (VLSIT), 2005 Symposium on, 2005


2004


Analysis and optimization of enhanced MTCMOS scheme
Rahul M Rao, Jeffrey L Burns, Richard B Brown
VLSI Design, 2004. Proceedings. 17th International Conference on, pp. 234--239

Analysis and mitigation of CMOS gate leakage
Rahul M Rao, Richard B Brown, Kevin Nowka, Jeffrey L Burns
Proceedings of the Fifth Annual Austin Center for Advanced Studies Conference, 7--11, Citeseer, 2004

Approaches to run-time and standby mode leakage reduction in global buses
Rahul Rao, Kanak Agarwal, Dennis Sylvester, Rebecca Brown, Kevin Nowka, Sani Nassif
Low Power Electronics and Design, 2004. ISLPED'04. Proceedings of the 2004 International Symposium on, pp. 188--193


2003

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies
Rahul M Rao, Jeffrey L Burns, Richard B Brown
Solid-State Circuits Conference, 2003. ESSCIRC'03. Proceedings of the 29th European, pp. 313--316

Leakage and leakage sensitivity computation for combinational circuits
Emrah Acar, Anirudh Devgan, Rahul Rao, Ying Liu, Haihua Su, Sani Nassif, Jeffrey Burns
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 96--99

A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits
Rahul M Rao, Frank Liu, Jeffrey L Burns, Richard B Brown
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, pp. 689

Efficient techniques for gate leakage estimation
Rahul M Rao, Jeffrey L Burns, Anirudh Devgan, Richard B Brown
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 100--103


2002

Low-Leakage Robust Circuit Design
Rahul Rao, Richard Brown
Proceedings of the Third Annual Austin Center for Advanced Studies Conference, 2002