Yutaka Nakamura  Yutaka Nakamura photo       

contact information

Research Staff Member
Research - Tokyo
  +81dash50dash3150dash3535

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2010

Time Division Multiplexed Limited Swing Dynamic Logic (LSDL)
Yutaka Nakamura, Rober K. Montoye and Lelang Chang


2009

Shared Bit Line SMT MRAM Array with Shunting Transistors Between the Bit Lines
H. Karl yang, Yutaka Nakamura and John K. Debrosse

Hybrid Bit-Line Architecture
Yutaka Nakamura and John K. DeBrosse


2007

Hybrid Static and Dynamic Sensing for Memory Arrays
Yutaka Nakamura, Rober K. Montoye and Lelang Chang


2006

An Ultra High-Speed NOR-type LDSL/Domino Combined Address Decoder
Yutaka Nakamura and Robert K. Montoye


2003

A Multiple shot Prefetch/Preload Method
Toshio Sunaga, Kohji Hosokawa, Hisatada Miyatake and Yutaka Nakamura

A Fast-Cycle Sense Amplifier for Low-Power DRAM Array
Yutaka Nakamura


2002

A Precharge-Before Access Mode
Toshio Sunaga, Yutaka Nakamura




Projects and Groups