Timothy J. Dalton  Timothy J. Dalton photo       

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CTO Science & Solutions, Member IBM Academy of Technology, Principal RSM & Master Inventor
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations:  American Vacuum Society

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2011

Semitubular metal-oxide-semiconductor field effect transistor
K Cheng, L A Clevenger, T J Dalton, L L Hsu, J A Mandelman, others
US Patent 7,868,374

INTERCONNECT STRUCTURE
Q LIN
WO Patent WO/2011/147,670

Flash memory gate structure for widened lithography window
K Cheng, L A Clevenger, T J Dalton, L L Hsu, others
US Patent 7,888,729

Phase change memory element with a peripheral connection to a thin film electrode
John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang, others
US Patent 7,923,712

Double-sided integrated circuit chips
K Bernstein, T Dalton, J P Gambino, M D Jaffe, P D Kartschoke, S E Luce, A K Stamper, others
US Patent 7,989,312


Dual-sided chip attached modules
K Bernstein, T Dalton, T H Daubenspeck, J P Gambino, M D Jaffe, C D Muzzy, W Sauter, E Sprogis, A K Stamper, others
US Patent 7,863,734


Dual wired integrated circuit chips
K Bernstein, T J Dalton, J P Gambino, M D Jaffe, P D Kartschoke, A K Stamper, others
US Patent 7,960,245

Three-dimensional networking structure
K Bernstein, T J Dalton, M R Faucher, P A Sandon
US Patent 7,865,694

High density planar magnetic domain wall memory apparatus
Michael C Gaidis, Lawrence A Clevenger, Timothy J Dalton, John K DeBrosse, Louis LC Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang, others
US Patent 8,023,305


2010


Structure for stochastic integrated circuit personalization
Lawrence A Clevenger, Matthew E Colburn, Timothy J Dalton, Michael C Gaidis, Louis LC Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang, others
US Patent 7,838,873

Method for forming slot via bitline for MRAM devices
Michael C Gaidis, Carl Radens, Lawrence A Clevenger, Timothy J Dalton, Louis LC Hsu, Keith Kwong Hon Wong, Chih-Chao Yang, others
US Patent 7,825,420

Method of fabricating a microelectromechanical system (MEMS) switch
L Hsu, T Dalton, L Clevenger, C Radens, K H Wong, C C Yang
US Patent 7,657,995

PHOTOVOLTAIC MODULE WITH A CONTROLLABLE INFRARED PROTECTION LAYER
L A Clevenger, T J Dalton, M Darnon, R Krause, G Pfeiffer, K Prettyman, C J Radens, B C Sapp
US Patent App. 12/887,156

MIM capacitor and method of fabricating same
C C Yang, L A Clevenger, T J Dalton, L C Hsu, others
US Patent 7,821,051

PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
C T Black, T J Dalton, B B Doris, C Radens
EP Patent 2,250,123


Electrical fuses and resistors having sublithographic dimensions
C T Black, M E Colburn, T J Dalton, D C Edelstein, W K Li, A K Stamper, H S Yang, others
US Patent 7,741,721

A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER
L Clevenger, T Dalton, M Hoinkis, S Kaldor, K Kumar, S Seo, A Simon, Y Wang, C Yang, H Yang, others
EP Patent 1,570,517

Air gap under on-chip passive device
A K Stamper, A K Chinthakindi, D D Coolbaugh, T J Dalton, D C Edelstein, E E Eshun, J P Gambino, W J Murphy, K Vaed, others
US Patent 7,662,722

Addressable hierarchical metal wire test methodology
K Chanda, L Clevenger, T J Dalton, L L C Hsu, C C Yang, others
US Patent 7,749,778

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
L Clevenger, T J Dalton, L Hsu, C Radens, V Ramachandran, K K H Wong, C C Yang
US Patent 7,851,321

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer
L A Clevenger, S R Chiras, T Dalton, J J Demarest, D N Dunn, C T Dziobkowski, P L Flaitz, M W Lane, J R Lloyd, D D Restaino, others
US Patent 7,820,559

Structure and method for self aligned vertical plate capacitor
A K Chinthakindi, D D Coolbaugh, T J Dalton, E E Eshun, J P Gambino, A K Stamper, R P Volant
US Patent 7,670,921


2009



Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
L Clevenger, T J Dalton, L Hsu, C Radens, V Ramachandran, K K H Wong, C C Yang
US Patent 7,531,407

Structure and method for stochastic integrated circuit personalization
Lawrence A Clevenger, Matthew E Colburn, Timothy J Dalton, Michael C Gaidis, Louis LC Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang, others
US Patent 7,544,578

Method of fabrication of interconnect structures
C C Yang, L A Clevenger, A P Cowley, T J Dalton, M H Yoon, others
US Patent 7,563,710

Method for policy-based, autonomically allocated storage
W.C. Arnold, D.M. Chess, M.V. Devarakonda, A. Segal, I.N. Whalley
US Patent 7,480,912

Planar vertical resistor and bond pad resistor and related method
D D Coolbaugh, T J Dalton, D C Edelstein, E E Eshun, J P Gambino, K S Petrarca, A K Stamper, R P Volant, others
US Patent 7,528,048

Methods of Forming Metal Oxide Nanostructures, and Nanostructures Thereof
H. Kim, R.D. Miller, O.H. Park
US Patent App. 12/496,784

Method for producing thermally matched probe assembly
T J Dalton, S R McKnight, G F Walker
US Patent 7,546,670

Wafer-to-wafer alignments
T J Dalton, J P Gambino, M D Jaffee, S E Luce, E J Sprogis, others
US Patent 7,474,104

Error detection and correction in semiconductor structures
T J Dalton, M R Faucher, P D Kartschoke, P A Sandon, others
US Patent 7,526,698

Back end interconnect with a shaped interface
L A Clevenger, A P Cowley, T J Dalton, M Hoinkis, S K Kaldor, E Kaltalioglu, K A Kumar, D C La Tulipe Jr, J Schacht, A H Simon, others
US Patent 7,494,915

Method of forming high density planar magnetic domain wall memory
Michael C Gaidis, Lawrence A Clevenger, Timothy J Dalton, John K DeBrosse, Louis LC Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang, others
US Patent 7,514,271

Multilayer interconnect structure containing air gaps and method for making
Christopher V Jahnes, Satyanarayana V Nitta, Kevin S Petrarca, Katherine L Saenger
US Patent 7,534,696


2008

DESIGN STRUCTURES FOR SEMICONDUCTOR STRUCTURES WITH ERROR DETECTION AND CORRECTION
T J Dalton, M R Faucher, P D Kartschoke, P A Sandon
US Patent App. 12/120,701

Micro-cavity MEMS device and method of fabricating same
L C Hsu, L A Clevenger, T J Dalton, C J Radens, K K H Wong, C C Yang
US Patent 7,394,332

ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
T J Dalton, W C Natzle, P W Pastel, R S Wise, H Yan, Y Zhang
US Patent App. 12/170,634



Methods of fabricating passive element without planarizing
A K Chinthakindi, T J Dalton, E E Eshun, J P Gambino, A K Stamper, K Vaed, others
US Patent 7,427,550

Structure and Method for Mosfet Gate Electrode Landing Pad
L A Clevenger, T J Dalton, L C Hsu, C Radens, K Wong, others
EP Patent 1,994,563



Method of forming an interconnect structure
Heidi Lee Baks, Shyng-Tsong Chen, Timothy Joseph Dalton, Nicholas Colvin Masi Fuller, Kaushik Arun Kumar
US Patent 7,358,182

Interconnect structures with encasing cap and methods of making thereof
K H Wong, L C Hsu, T J Dalton, C Radens, C C Yang, L A Clevenger, T E Standaert
US Patent App. 12/199,407

STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH
L C Hsu, T Dalton, L Clevenger, C Radens, K H Wong, C C Yang
US Patent 7,348,870


Closed air gap interconnect structure
Matthew E Colburn, Timothy J Dalton, Elbert Huang, Simon M Karecki, Satya V Nitta, Sampath Purushothaman, Katherine L Saenger, Maheswaran Surendra
US Patent 7,361,991

Method of forming closed air gap interconnects and structures formed thereby
Matthew E Colburn, Timothy J Dalton, Elbert Huang, Simon M Karecki, Satya V Nitta, Sampath Purushothaman, Katherine L Saenger, Maheswaran Surendra
US Patent 7,393,776

Device and methodology for reducing effective dielectric constant in semiconductor devices
Daniel C Edelstein, Matthew E Colburn, Edward C Cooney III, Timothy J Dalton, John A Fitzsimmons, Jeffrey P Gambino, Elbert E Huang, Michael W Lane, Vincent J McGahay, Lee M Nicholson, others
US Patent 7,405,147

METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES
R P Volant, J C Bisson, D R Cote, T J Dalton, R A Groves, K S Petrarca, K J Stein, S Subbanna
EP Patent 1,461,828

Interconnect structures and methods of making thereof
C C Yang, L L Hsu, K K H Wong, T J Dalton, C Radens, L Clevenger, others
US Patent 7,365,001

Integrated Circuit Comb Capacitor
D C Edelstein, A K Chinthakindi, T J Dalton, E E Eshun, J P Gambino, S L Lane, A K Stamper
US Patent App. 12/034,728


2007

High density planar magnetic domain wall memory apparatus and method of forming the same
Lawrence A Clevenger, Timothy J Dalton, John K DeBrosse, Michael C Gaidis, Louis LC Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
US Patent App. 11/694,183

CORRUGATED INTERFACES FOR MULTILAYERED INTERCONNECTS
L A Clevenger, T J Dalton, E E Huang, S Purushothaman, C J Radens
US Patent App. 11/836,253

Method of forming low resistance and reliable via in inter-level dielectric interconnect
C Cabral Jr, L A Clevenger, T J Dalton, P W DeHaven, C T Dziobkowski, S Fang, T A Spooner, T L L Tai, K H Wong, C C Yang, others
US Patent 7,223,691



Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter
Charles T Black, Gian-Luca Bona, Timothy J Dalton, Nicholas CM Fuller, Roland Germann, Maurice McGlashan-Powell, Chandrasekhar Narayan, Robert L Sandstrom
US Patent 7,298,935



MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT
L A Clevenger, T J Dalton, L C Hsu, C E Murray, C Radens, K H Wong, C C Yang
US Patent App. 11/839,258

Bilayered metal hardmasks for use in dual damascene etch schemes
K Kumar, L Clevenger, T Dalton, D C La Tulipe, A Cowley, E Kaltalioglu, J Schacht, A H Simon, M Hoinkis, S K Kaldor, others
US Patent 7,241,681

INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME
C Yang, L A Clevenger, A P Cowley, T J Dalton, M H Yoon
EP Patent 1,869,700

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
L Clevenger, T J Dalton, M Hoinkis, S K Kaldor, K Kumar, D C La Tulipe Jr, S C Seo, A H Simon, Y Y Wang, C C Yang, others
US Patent 7,241,696


2006

De-fluorination of wafer surface and related structure
Timothy J Dalton, Nicholas CM Fuller, Kaushik A Kumar, Catherine Labelle
US Patent 7,049,209

Crystallographic modification of hard mask properties
L A Clevenger, A P Cowley, T J Dalton, M Hoinkis, S K Kaldor, K A Kumar, S M Rossnagel, A H Simon, D C La Tulipe Jr, others
US Patent 7,001,835

Method for adjusting capacitance of an on-chip capacitor
L A Clevenger, T J Dalton, L L Hsu, C Radens, K K H Wong, C C Yang, others
US Patent 7,092,235

Nano-scaled gate structure with self-interconnect capabilities
L A Clevenger, T J Dalton, L L Hsu, C Radens, K K H Wong, C C Yang, others
US Patent 7,115,921

Method of forming a MIM capacitor for Cu BEOL application
C C Yang, T Dalton, L Clevenger, G Matusiewicz
US Patent 7,091,542

Dual damascene structure and method
K Kumar, D C La Tulipe, T Dalton, L Clevenger, A Cowley, E Kaltalioglu, J Schacht, others
US Patent 7,125,792

Very low effective dielectric constant interconnect Structures and methods for fabricating the same
Donald F Canaperi, Timothy J Dalton, Stephen M Gates, Mahadevaiyer Krishnan, Satya V Nitta, Sampath Purushothaman, Sean PE Smith
US Patent 7,023,093

Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof
John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang
US Patent App. 11/394,263

CD uniformity of chrome etch to photomask process
S B Crawford, T J Dalton, T B Faure, C K Huynh, M L Steen, T M Wagner, others
US Patent 7,014,959

Copper recess process with application to selective capping and electroless plating
S T Chen, T J Dalton, K M Davis, C K Hu, F F Jamin, S K Kaldor, M Krishnan, K Kumar, M F Lofaro, S G Malhotra, others
US Patent 7,064,064

Line level air gaps
Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, others
US Patent 7,084,479

Method for dry etching photomask material
T J Dalton, T B Faure, M L Steen, others
US Patent 7,014,958

Method and structure for forming slot via bitline for mram devices
Lawrence A Clevenger, Timothy J Dalton, Michael C Gaidis, Louis LC Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
WO Patent App. PCT/US2006/028,718

Deep filled vias
Panayotis Andricacos, Emanuel Israel Cooper, Timothy Joseph Dalton, Hariklia Deligianni, Daniel Guidotti, Keith Thomas Kwietniak, Michelle Leigh Steen, Cornelia Kang-I Tsang
US Patent 7,060,624


2005


ETCHING APPARATUS FOR SEMICONDUCTOR FABRICATION
T J Dalton, E F Gallagher, L M Kindt, C W Thiel, A J Watts
US Patent App. 10/906,627


Damascene interconnect structures including etchback for low-k dielectric materials
A K Stamper, E C Cooney III, J P Gambino, T J Dalton, J A Fitzsimmons, L M Nicholson
US Patent 6,838,355

Interconnect structure improvements
T J Dalton, J A Fitzsimmons, J P Gambino, L M Nicholson, A H Simon, A K Stamper, others
US Patent 6,960,519

Fuse structure and method to form the same
D K Anderson, T J Cheng, T J Dalton, C V Jahnes, A Lu, C Narayan, K S Petrarca, R P Volant, G F Walker, others
US Patent 6,924,185

Method for protecting a semiconductor device from carbon depletion based damage
Griselda Bonilla, Richard Conti, Timothy Dalton, Nicholas Fuller, Kelly Malone, Satyanarayana Nitta, Shom Ponoth
US Patent App. 11/162,219


2004

OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING
W G America, L Clevenger, A Cowley, T J Dalton, M Hoinkis, K A Kumar, D C La Tulipe
US Patent App. 10/708,648

Apparatus and Method of Intelligent Multistage System Deactivation
L C Hsu, L A Clevenger, C J Radens, K H Wong, C C Yang, T J Dalton
US Patent App. 10/904,664


Self-contained heat sink and a method for fabricating same
T J Dalton, K S Petrarca, M L Steen, C K Tsang, R P Volant
US Patent 6,815,813

FILLED CAVITIES SEMICONDUCTOR DEVICES
T J Dalton, J A Fitzsimmons, A K Stamper
US Patent App. 10/708,883

Fine-pitch device lithography using a sacrificial hardmask
Timothy J Dalton, Minakshisundaran B Anand, Michael D Armacost, Shyng-Tsong Chen, Stephen M Gates, Stephen E Greco, Simon M Karecki, Satyanarayana V Nitta
US Patent 6,734,096

Diffusion barrier layer and semiconductor device containing same
S A Cohen, T J Dalton, J A Fitzsimmons, S M C Gates, L M Gignac, P C Jamison, K W Lee, S Purushothaman, D D Restaino, E Simonyi, others
US Patent 6,784,485

Structure and method for reducing thermo-mechanical stress in stacked vias
T J Dalton, S K Das, B H Engel, B W Herbst, H Hichri, B E Kastenmeier, K Malone, J R Marino, A Martin, V J McGahay, others
US Patent 6,831,363

Protective hardmask for producing interconnect structures
T J Dalton, C V Jahnes, J C Liu, S Purushothaman
US Patent 6,720,249


2003



Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
W Cote, T J Dalton, D C Edelstein, S M C Gates
US Patent 6,548,901

Partial inter-locking metal contact structure for semiconductor devices and method of manufacture
C C Yang, L A Clevenger, T J Dalton, L L C Hsu, C Radens, K K H Wong
US Patent App. 10/723,152


Process for forming a damascene structure
W J Cote, T J Dalton, P C Dev, D C Edelstein, S D Halle, G Y Lee, A P Mahorowala, others
US Patent 6,649,531

Interconnect structures containing stress adjustment cap layer
S M Gates, T J Dalton, J A Fitzsimmons
US Patent 6,617,690


2002

Method for forming a porous dielectric material layer in a semiconductor device and device formed
Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
US Patent 6,451,712


Method of forming an on-chip decoupling capacitor with bottom hardmask
T J Dalton, A P Cowley, P A Emmi, E Kaltalioglu, V J McGahay, others
US Patent 6,387,754



2001

Low k dielectric film deposition process
D C Edelstein, W J Cote, T J Dalton, C V Jahnes, G Y Lee
US Patent App. 10/005,861

Spin-on cap layer, and semiconductor device containing same
Timothy Dalton, Stephen Gates, Jeffrey Hedrick, Satyanarayana Nitta, Sampath Purushothaman, Christy Tyberg

On-chip decoupling capacitor with bottom hardmask
T J Dalton, A P Cowley, P A Emmi, E Kaltalioglu, V J McGahay
US Patent 6,278,147


1998



1995



Year Unknown