Takashi Ando  Takashi Ando photo       

contact information

Research Staff Member, Master Inventor
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)  |  The Japan Society of Applied Physics


2017

High Mobility High-Ge-Content SiGe PMOSFETs Using Al 2 O 3/HfO 2 Stacks With In-Situ O 3 Treatment
Ando, Takashi and Hashemi, Pouya and Bruley, John and Rozen, John and Ogawa, Yohei and Koswatta, Siyuranga and Chan, Kevin K and Cartier, Eduard A and Mo, Renee and Narayanan, Vijay
IEEE Electron Device Letters 38(3), 303--305, IEEE, 2017
Abstract

High performance PMOS with strained high-Ge-content SiGe fins for advanced logic applications
Hashemi, Pouya and Ando, Takashi and Balakrishnan, Karthik and Koswatta, Siyuranga and Lee, Kam-Leung and Ott, John A and Chan, Kevin and Bruley, John and Engelmann, Sebastian U and Narayanan, Vijay and others
VLSI Technology, Systems and Application (VLSI-TSA), 2017 International Symposium on, pp. 1--2


2016

High-k Oxides on Si: MOSFET Gate Dielectrics
Ando, Takashi and Kwon, Unoh and Krishnan, Siddarth and Frank, Martin M and Narayanan, Vijay
Thin Films on Silicon: Electronic and Photonic Applications8, 323, World Scientific, 2016
Abstract

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations
Hashemi, Pouya and Balakrishnan, Karthik and Ando, Takashi and Bruley, John and Ott, John A and Engelmann, Sebastian and Chan, Kevin and Lee, Kam-Leung and Park, Dae-Gyu and Mo, Renee T and others
ECS Transactions 75(8), 39--50, The Electrochemical Society, 2016
Abstract

(Invited) CMOS Compatible High Performance IIIV Devices: Opportunities and Challenges
Sun, Yanning and Shiu, Kuen-Ting and Cheng, Cheng-Wei and Majumdar, Amlan and Bruce, Robert and Yau, Jeng-bang and Farmer, Damon and Zhu, Yu and Hopstaken, Marinus and Frank, Martin M and others
ECS Transactions 72(4), 313--319, The Electrochemical Society, 2016
Abstract

Demonstration of record SiGe transconductance and short-channel current drive in High-Ge-Content SiGe PMOS FinFETs with improved junction and scaled EOT
Hashemi, Pouya and Lee, Kam-Leung and Ando, Takashi and Balakrishnan, Karthik and Ott, John A and Koswatta, Syuranga and Engelmann, Sebastian U and Park, Dae-Gyu and Narayanan, Vijay and Mo, Renee T and others
VLSI Technology, 2016 IEEE Symposium on, pp. 1--2
Abstract


2015

Evolution of interfacial Fermi level in In0. 53Ga0. 47As/high-$\kappa$/TiN gate stacks
Carr, Adra and Rozen, John and Frank, Martin M and Ando, Takashi and Cartier, Eduard A and Kerber, Pranita and Narayanan, Vijay and Haight, Richard
Applied Physics Letters 107(1), 012103, AIP Publishing, 2015
Abstract


2014

A Simulation Study of Oxygen Vacancy-Induced Variability in $$\{$$\backslash$ rm HfO$\}$ \_ $\{$2$\}$ $/Metal Gated SOI FinFET
Trivedi, Amit Ranjan and Ando, Takashi and Singhee, Amith and Kerber, Pranita and Acar, Emrah and Frank, David J and Mukhopadhyay, Saibal
IEEE Transactions on Electron Devices 61(5), 1262--1269, IEEE, 2014
Abstract

Atomic Layer Deposition of Sidewall Spacers: Process, Equipment and Integration Challenges in State-of-the-Art Logic Technologies
Belyansky, Michael P and Conti, Richard and Khan, Shahrukh and Zhou, Xin and Klymko, Nancy R and Yao, Yiping and Madan, Anita and Tai, Leo and Flaitz, Philip and Ando, Takashi
ECS Transactions 61(3), 39--45, The Electrochemical Society, 2014
Abstract

Combined Ramp Voltage Stress and Constant Voltage Stress for optimal BTI voltage acceleration and lifetime modeling
Linder, Barry P and Ando, Takashi
Reliability Physics Symposium, 2014 IEEE International, pp. XT--7
Abstract

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs
Frank, Martin M and Zhu, Yu and Bedell, Stephen W and Ando, Takashi and Narayanan, Vijay
ECS Transactions 61(2), 213--223, The Electrochemical Society, 2014
Abstract

CMOS Scaling Enabled by High-k/Metal Gate Technology: Planer to 3-D Structures (invited)
Takashi Ando
67th Ultra Precision Workshop, 2014


2013

Origins of effective work function roll-off behavior for high-$\kappa$ last replacement metal gate stacks
Ando, Takashi and Cartier, Eduard A and Bruley, John and Choi, Kisik and Narayanan, Vijay
IEEE Electron Device Letters 34(6), 729--731, IEEE, 2013
Abstract

(Invited) The Past, Present and Future of High-k/Metal Gates
Choi, Kisik and Ando, Takashi and Cartier, Eduard A and Kerber, Andreas and Paruchuri, Vamsi and Iacoponi, John and Narayanan, Vijay
ECS Transactions 53(3), 17--26, The Electrochemical Society, 2013
Abstract

Material and Process Considerations for Ultimate EOT Scaling of High-k/Metal Gate Stacks (invited)
Takashi Ando
18th Conference of "Insulating Films on Semiconductors", 2013

Higher-k stack using a TiO2 capping layer compatible with gate last processing to achieve 7A EOT with reduced leakage, suppressed EWF roll-off, and improved reliability
J. Rozen, T. Ando, E. Cartier, M. M. Frank, S. L. Brown, J. Bruley, A. J. Kellock, and V. Narayanan
44th IEEE Semiconductor Interface Specialists Conference, pp. 11-9, 2013

The past, present and future of high-k/metal gates
Kisik Choi, Takashi Ando, Martin Frank, Eduard Cartier, Vamsi Paruchuri, John Iacoponi, Vijay Narayanan
223rd ECS Meeting, 2013

Characterization and Optimization of Dielectric Relaxation in High-K Dielectrics
E. Cartier, R. Krishnan, A. Kerber, S. De, R. Pandey, T. Ando, M. Hopstaken, J. F. Shepard, M. D. Sullivan, K. Murali, S. Krishnan, V. Narayanan, M. P. Chudzik
IEEE International Reliability Physics Symposium, pp. 5A.2, 2013

Origins of Effective Work Function Roll-Off Behavior for High-k Last Replacement Metal Gate Stacks
Takashi Ando, Eduard A. Cartier, John Bruley, Kisik Choi, and Vijay Narayanan
IEEE Electron Device Lett. 34(6), 729, 2013

Aggressive SiGe channel gate stack scaling by remote oxygen scavenging: Gate-first pFET performance and reliability
Martin M. Frank, Eduard A. Cartier, Takashi Ando, Stephen W. Bedell, John Bruley, Yu Zhu, Vijay Narayanan
ECS Solid State Lett. 2(2), N8-N10, The Electrochemical Society, 2013

Characterization and optimization of charge trapping in high-k dielectrics
Cartier, Eduard and Ando, Takashi and Hopstaken, Marinus and Narayanan, Vijay and Krishnan, Rishikesh and Shepard, Joseph F and Sullivan, Michael D and Krishnan, Siddarth and Chudzik, Michael P and De, Sandip and others
Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. 5A--2
Abstract


2012

The Interaction Challenges with Novel Materials in Developing High-Performance and Low-Leakage High-k/Metal Gate CMOS Transistors
Chudzik, Michael and Krishnan, Siddarth and Kwon, Unoh and Khare, Mukesh and Narayanan, Vijay and Ando, Takashi and Cartier, Ed and Bu, Huiming and Paruchuri, Vamsi
High-k Gate Dielectrics for CMOS Technology, 531--555, Wiley Online Library, 2012
Abstract

Ultimate Scaling of High-k Gate Dielectrics: Current Status and Challenges (invited)
Takashi Ando
AVS 59th International Symposium & Exhibition, 2012

Ultimate Scaling of High-k Gate Dielectrics: Current Status and Challenges (invited)
Takashi Ando
International Conference on Solid State Devices and Materials, 2012

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: pFET Performance and Reliability
Martin M. Frank, Eduard A. Cartier, Takashi Ando, Stephen W. Bedell, John Bruley, Yu Zhu, Vijay Narayanan
222nd ECS Meeting, pp. 2615, 2012

Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniques
M.J.P. Hopstaken, D. Pfeiffer, M. Copel, M.S. Gordon, T. Ando, V. Narayanan, H. Jagannathan, S. Molis, J.A. Wahl, H. Bu, D.K. Sadana, L. Czornomaz, C. Marchiori, J. Fompeyrine
Surface and Interface Analysis 45(1), 338-344, 2012

Bias temperature instability in High-$\kappa$/metal gate transistors-Gate stack scaling trends
Siddarth Krishnan, Vijay Narayanan, Eduard Cartier, Dimitris Ioannou, Kai Zhao, Takashi Ando, Unoh Kwon, Barry Linder, James Stathis, Michael Chudzik, others
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 5A--1

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, P Parries, T Ando, M Aquilino, N Arnold, others
Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 3--3

Ultimate Scaling of High-$\kappa$ Gate Dielectrics: Higher-$\kappa$ or Interfacial Layer Scavenging?
T Ando
Materials 5(3), 478--500, Molecular Diversity Preservation International, 2012

Bias temperature instability in High-$\kappa$/metal gate transistors-Gate stack scaling trends
Krishnan, Siddarth and Narayanan, Vijay and Cartier, Eduard and Ioannou, Dimitris and Zhao, Kai and Ando, Takashi and Kwon, Unoh and Linder, Barry and Stathis, James and Chudzik, Michael and others
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 5A--1
Abstract

The Interaction Challenge Between CMOS Integration and Novel Materials in Developing High Performance and Low Leakage High-k/Metal Gate Transistors
M. Chudzik, S. Krishnan, U. Kwon, M. Khare, V. Narayanan, T. Ando, E. Cartier, H. Bu, and V. Paruchuri
High-k Gate Dielectrics for CMOS Technology, pp. 531-555, Wiley-VCH Verlag GmbH & Co. KGaA, 2012

Ultimate scaling of high-$\kappa$ gate dielectrics: Higher-$\kappa$ or interfacial layer scavenging?
Ando, Takashi
Materials 5(3), 478--500, Molecular Diversity Preservation International, 2012
Abstract


2011

(Invited) Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies
Cartier, Eduard and Kerber, Adreas and Krishnan, Siddarth and Linder, Barry and Ando, Takashi and Frank, Martin M and Choi, Kisik and Narayanan, Vijay
ECS Transactions 41(3), 337--348, The Electrochemical Society, 2011
Abstract

Mechanism of V FB/V TH shift in dysprosium incorporated HfO 2 gate dielectric n-type metal-oxide-semiconductor devices
Lee, Tackhwi and Choi, Kisik and Ando, Takashi and Park, Dae-Gyu and Gribelyuk, Michael A and Kwon, Unoh and Banerjee, Sanjay K
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 29(2), 021209, AVS, 2011
Abstract

Maximized Benefit of La--Al--O Higher-$ k $ Gate Dielectrics by Optimizing the La/Al Atomic Ratio
Arimura, Hiroaki and Brown, Stephen L and Callegari, Alessandro and Kellock, Andrew and Bruley, John and Copel, Matt and Watanabe, Heiji and Narayanan, Vijay and Ando, Takashi
IEEE Electron Device Letters 32(3), 288--290, IEEE, 2011
Abstract

Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, K Zhao, F Monsieur, J Stathis, others
Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 18--4


Maximized Benefit of La--Al--O Higher-$ k $ Gate Dielectrics by Optimizing the La/Al Atomic Ratio
H Arimura, S L Brown, A Callegari, A Kellock, J Bruley, M Copel, H Watanabe, V Narayanan, T Ando
Electron Device Letters, IEEE 32(3), 288--290, IEEE, 2011

On the Electron and Hole Tunneling in a $ hbox $\{$HfO$\}$ \_ $\{$2$\}$ $ Gate Stack With Extreme Interfacial-Layer Scaling
T Ando, N D Sathaye, K V R M Murali, E A Cartier
Electron Device Letters, IEEE pp. 99, 1--3, IEEE, 2011

A Manufacturable Dual Channel (Si and SiGe) High-K Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications
S. Krishnan, U. Kwon, N. Moumen, M. Stoker, E. C. Harley, S. W. Bedell, D. R. Nair, B. J. Greene, W. K. Henson, M. M. Chowdhury, D. P. Prakash, E. Wu, D. P. Ioannou, E. Cartier, M.-h. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Har
International Electron Devices Meeting, pp. 28-1, 2011

Work function control and equivalent oxide thickness scaling below 9A in a LaAlO-silicate interfacial layer / HfO2 stack compatible with gate last processing
J. Rozen, T. Ando, S.L. Brown, J. Bruley, E. Cartier, A.J. Kellock, and V. Narayanan
42nd IEEE Semiconductor Interface Specialists Conference, pp. P.1, 2011

Origin of Effective Work Function Roll-off Behavior for Replacement Gate Process Studied by Low-temperature Interfacial Layer Scavenging Technique
Takashi Ando, Eduard Cartier, John Bruley, Kisik Choi, and Vijay Narayanan
42nd IEEE Semiconductor Interface Specialists Conference, pp. 1-2, 2011

EOT scaling strategy for 22nm and beyond: Higher-k or interfacial layer scavenging? (invited)
T. Ando, M. M. Frank, K. Choi, J. Rozen, J. Bruley, and V. Narayanan
8th International Symposium on Advanced Gate Stack Technology, 2011

Mechanism of VFB/VTH shift in Dysprosium incorporated HfO2 gate dielectric n-Type Metal-Oxide-Semiconductor devices
Tackhwi Lee, Kisik Choi, Takashi Ando, Dae-Gyu Park, Michael A. Gribelyuk, Unoh Kwon, and Sanjay K. Banerjee
J. Vac. Sci. Technol. B29, 021209, 2011

On the Electron and Hole Tunneling in a $$\backslash$ hbox $\{$HfO$\}$ \_ $\{$2$\}$ $ Gate Stack With Extreme Interfacial-Layer Scaling
Ando, Takashi and Sathaye, Ninad D and Murali, Kota VRM and Cartier, Eduard A
IEEE Electron Device Letters 32(7), 865--867, IEEE, 2011
Abstract


2010

(Invited) Ultimate EOT Scaling (< 5A{\aa}) Using Hf-Based High-$\kappa$ Gate Dielectrics and Impact on Carrier Mobility
Ando, Takashi and Frank, Martin M and Choi, Kisik and Choi, Changhwan and Bruley, John and Hopstaken, Marinus J and Haight, Richard and Copel, Matthew and Arimura, Hiroaki and Watanabe, Heiji and others
ECS Transactions 28(1), 115--123, The Electrochemical Society, 2010
Abstract

Ultimate EOT Scaling (< 5A{\aa}) Using Hf-Based High-$\kappa$ Gate Dielectrics and Impact on Carrier Mobility
Ando, Takashi and Frank, Martin M and Choi, Kisik and Choi, Changhwan and Bruley, John and Hopstaken, Marinus and Copel, Matthew and Haight, Richard and Arimura, Hiroaki and Watanabe, Heiji and others
Meeting Abstracts, pp. 927--927, 2010
Abstract

High-k/Metal Gate Technology: Dipoles, Vacancies and Pathway for EOT Scaling
T. Ando, K. Choi, H. Jagannathan, C. Choi, E. Cartier, B. P. Linder, and V. Narayanan
JSAP 15th Gate Stack Conference, 2010

Interfacial Layer Scaling Strategies for Metal Gate / High-k Stacks on Silicon
Martin M. Frank, Takashi Ando, Changhwan Choi, Kisik Choi, and Vijay Narayanan
MRS Spring Meeting , 2010

Optimization of composition ratio in La-Al-O gate dielectrics for advanced metal/higher-k devices
H. Arimura, T. Ando, S. Brown, A. Kellock, A. Callegari, M. Copel, R. Haight, H. Watanabe, and V. Narayanan
MRS Spring Meeting , 2010

High-k/Metal Gate Technology: Dipoles, Vacancies and Pathway for EOT Scaling
T. Ando, K. Choi, H. Jagannathan, E. Cartier, B. P. Linder, M. M. Frank, and V. Narayanan
SEMATECH International Symposium on Advanced Gate Stack Technology , 2010

Plenty of Room at the Bottom: Scaling the High-k/Silicon Interfacial Layer
Martin M. Frank, Takashi Ando, Kisik Choi, Changhwan Choi, John Bruley, Chiara Marchiori, Jean Fompeyrine, and Vijay Narayanan
16th Workshop on Dielectrics in Microelectronics , 2010

Impact of La and Al Composition Ratio on the Electrical Properties of La-Al-O Higher-k Gate Dielectrics
H. Arimura, T. Ando, S. L. Brown, A. Kellock, A. Callegari, M. Copel, R. Haight, H. Watanabe, and V. Narayanan
Third International Symposium on Atomiscally Controlled Fabrication Technology, 2010

Kinetics of interfacial layer scavenging and dipole formation for ultimate scaling of Hf-based high-k gate dielectrics
Takashi Ando, Hiroaki Arimura, Richard Haight, Matt Copel, Heiji Watanabe, and Vijay Narayanan
41st IEEE Semiconductor Interface Specialists Conference, 2010

Ultimate EOT Scaling (< 5A) Using Hf-based High-k Gate Dielectrics and Impact on Carrier Mobility (invited)
Takashi Ando, Martin M. Frank, Kisik Choi, Changhwan Choi, Richard Haight, Matt Copel, Hiroaki Arimura, Heiji Watanabe, and Vijay Narayanan
ECS Trans. 28(1), 115, 2010


Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO2 Gate Stack Fabricated by Gate-Last Process
T Ando, T Hirano, K Tai, S Yamaguchi, S Yoshida, H Iwamoto, S Kadomura, H Watanabe
Japanese Journal of Applied Physics 49(1), 6502, Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physics, 2010

Physical origins of mobility degradation in extremely scaled SiO 2/HfO 2 gate stacks with La and Al induced dipoles
Ando, Takashi and Copel, Matt and Bruley, John and Frank, Martin M and Watanabe, Heiji and Narayanan, Vijay
Applied Physics Letters 96(13), 132904, AIP, 2010
Abstract

Temperature-dependent La-and Al-induced dipole behavior monitored by femtosecond pump/probe photoelectron spectroscopy
H Arimura, R Haight, S L Brown, A Kellock, A Callegari, M Copel, H Watanabe, V Narayanan, T Ando
Applied Physics Letters96, 132902, 2010

Oxygen Transport in High-k Metal Gate Stacks and Physical Characterization by SIMS Using Isotopic Labeled Oxygen
M J Hopstaken, J Bruley, D Pfeiffer, M Copel, M M Frank, E Cartier, T Ando, V Narayanan
ECS Trans. 28(1), 105, The Electrochemical Society, 2010


2009

Band-Edge High-Performance Metal-Gate/High-$$\backslash$ kappa $ nMOSFET Using $$\backslash$ hbox $\{$Hf$\}$$\{$-$\}$$\backslash$ hbox $\{$Si$\}$/$\backslash$ hbox $\{$HfO$\}$ \_ $\{$2$\}$ $ Stack
Ando, Takashi and Hirano, Tomoyuki and Tai, Kaori and Yamaguchi, Shinpei and Yoshida, Shinichi and Iwamoto, Hayato and Kadomura, Shingo and Watanabe, Heiji
IEEE Transactions on Electron Devices 56(12), 3223--3227, IEEE, 2009
Abstract

Novel Single Metal Gate CMOS Integration with Effective Workfunction Modulation by a Differential Spacer:Manipulation of Oxygen Vacancy
Y. H. Kim, K. Schonenberg, T. Ando, D. Neumayer, R. Mo, H. Bu, J. Sleight, E. Cartier, N. Moumen, R. Jha, W. Yan, Y. Liang, V. Narayanan, M. P. Chudzik, and S. Guha
The International Conference on Solid State Devices and Materials, 2009

Effective Work Function Control of TaC/High-k Gate Stack by Post Metal Nitridation
Takashi Ando, Alessandro Callegari, Changhwan Choi, Marinus Hopstaken, John Bruley, Michael Gordon, Heiji Watanabe, and Vijay Narayanan
40th IEEE Semiconductor Interface Specialists Conference, 2009

pFET Vt control with HfO2/TiN/poly-Si gate stack using a lateral oxygenation process
E Cartier, M Steen, BP Linder, T Ando, R Iijima, M Frank, JS Newbury, YH Kim, FR McFeely, M Copel, others
VLSI Technology, 2009 Symposium on, pp. 42--43

Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process
T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, E Cartier, A Kerber, A Callegari, others
Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1--4

Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
K Choi, Hi Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, M Wang, E Cartier, S Zafar, others
VLSI Technology, 2009 Symposium on, pp. 138--139

Mechanism of Carrier Mobility Degradation Induced by Crystallization of HfO2 Gate Dielectrics
T Ando, T Shimura, H Watanabe, T Hirano, S Yoshida, K Tai, S Yamaguchi, H Iwamoto, S Kadomura, S Toyoda, others
Applied Physics Express 2(7), 1402, 2009

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes
C Choi, T Ando, E Cartier, M M Frank, R Iijima, V Narayanan
Microelectronic Engineering 86(7-9), 1737--1739, Elsevier, 2009

Band-Edge High-Performance Metal-Gate/High-k nMOSFET Using Hf-Si/HfO2 Stack
T Ando, T Hirano, K Tai, S Yamaguchi, S Yoshida, H Iwamoto, S Kadomura, H Watanabe
Electron Devices, IEEE Transactions on 56(12), 3223--3227, IEEE, 2009


2008

Modulating Work Function for pFET with AVD Ru-based & TaN-based Gate Electrodes
C. Choi, T. Ando, Z. Karim, S. Ramanathan, and V. Narayanan
39th IEEE Semiconductor Interface Specialists Conference , 2008

Channel-stress study on gate-size effects for damascene-Gate pMOSFETs with top-cut compressive stress liner and eSiGe
S Mayuzumi, S Yamakawa, D Kosemura, M Takei, J Wang, T Ando, Y Tateshita, M Tsukamoto, H Wakabayashi, T Ohno, others
VLSI Technology, 2008 Symposium on, pp. 126--127

Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone--Water-Last Treatment
I Oshiyama, K Tai, T Hirano, S Yamaguchi, K Tanaka, Y Hagimoto, T Uemura, T Ando, K Watanabe, R Yamamoto, others
Jpn J Appl Phys 47(4), 2379--2382, Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physics, 2008

Threshold Voltage Modulation Technique using Fluorine Treatment through Atomic Layer Deposition TiN Suitable for Complementary Metal-Oxide-Semiconductor Devices
K Tai, S Yamaguchi, K Tanaka, T Hirano, I Oshiyama, S Kazi, T Ando, M Nakata, M Yamanaka, R Yamamoto, others
Japanese Journal of Applied Physics 47(4part2), 2345--2348, 2008


2007

High-Performance High-k/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing
M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, W Natzle, W Yan, others
2007 IEEE Symposium on VLSI Technology, pp. 194--195

Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application (invited)
Takashi Ando
JSAP 12th Gate Stack Conference, 2007

Opportunities and Challenges of ALD for CMOS Devices in 45-nm Generation and Beyond (invited)
Takashi Ando
7th International Conference on Atomic Layer Deposition, 2007

High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates
Y Tateshita, J Wang, K Nagano, T Hirano, Y Miyanami, T Ikuta, T Kataoka, Y Kikuchi, S Yamaguchi, T Ando, others
IEEE International Electron Devices Meeting, pp. 1--4, 2007

Materials and process integration issues in metal gate/high-k stacks and their dependence on device performance
Alessandro Callegari, Katherina Babich, Sufi Zafar, Vijay Narayanan, Takashi Ando, Philip E Batson
ECS Transactions 11(4), 265--274, The Electrochemical Society, 2007

High Performance and High Reliability Dual Metal CMOS Gate Stacks Using Novel High-k Bi-layer Control Technique
T Ando, T Hirano, K Tai, S Yamaguchi, K Tanaka, I Oshiyama, M Nakata, K Watanabe, R Yamamoto, S Kanda, others
VLSI Technology, Systems and Applications, 2007, pp. 1--2


2006

Physical and Electrical Characterization of HfSix/HfO2 Gate Stacks for High-Performance nMOSFET Application
S. Yoshida, Y. Kita, T. Ando, K. Tai, H. Iwamoto, T. Shimura, H. Watanabe and K. Yasutake
37th IEEE Semiconductor Interface Specialists Conference , 2006

Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application
T Ando, T Hirano, K Tai, S Yamaguchi, T Kato, Y Hagimoto, K Watanabe, R Yamamoto, S Kanda, K Nagano, others
VLSI Technology, 2006, pp. 166--167

High performance dual metal gate CMOS with high mobility and low threshold voltage applicable to bulk CMOS technology
S Yamaguchi, K Tai, T Hirano, T Ando, S Hiyama, J Wang, Y Hagimoto, Y Nagahama, T Kato, K Nagano, others
VLSI Symposium, 192--192, 2006

Application of HfSiON to Deep-Trench Capacitors of Sub-45-nm-Node Embedded Dynamic Random-Access Memory
T Ando, N Sato, S Hiyama, T Hirano, K Nagaoka, H Abe, A Okuyama, H Ugajin, K Tai, S Fujita, others
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1 REGULAR PAPERS SHORT NOTES AND REVIEW PAPERS 45(4B), 3165, Japanese Journal of Applied Physics, 2006

High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process
K Tai, T Hirano, S Yamaguchi, T Ando, S Hiyama, J Wang, Y Nagahama, T Kato, M Yamanaka, S Terauchi, others
ESSDERC, pp. 121--124, 2006


2005

High performance nMOSFET with HfSix/HfO 2 gate stack by low temperature process
T Hirano, T Ando, K Tai, S Yamaguchi, T Kato, S Hiyama, Y Hagimoto, S Takesako, N Yamagishi, K Watanabe, others
IEEE International Electron Devices Meeting, 2005, pp. 890--893

Nitrogen doping and thermal stability in HfSiON studied by photoemission and x-ray absorption spectroscopy
S Toyoda, J Okabayashi, H Takahashi, M Oshima, D I Lee, S Sun, S Sun, P A Pianetta, T Ando, S Fukuda
Applied Physics Letters87, 182908, 2005


2002

Spectroscopic Studies of Rare-Earth-Doped BaTiO3 Luminescent Gels
Hirofumi Matsuda, Takashi Ando, Kun'ichi Miyazawa, Makoto Kuwabara
Key Eng. Mater.216, 57-60, 2002


2001

Grain-size Effect on the Structure and Properties of BaTiO3 Fabricated by Sol-gel Method
Takashi Ando, Hirofumi Matsuda, Kunnichi Miyazawa, and Makoto Kuwabara
Trans. Mater. Res. Soc. Jpn. 26(1), 95, 2001