Takashi Ando  Takashi Ando photo       

contact information

Research Staff Member, Master Inventor
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)  |  The Japan Society of Applied Physics


2017

Trench metal-insulator-metal capacitor with oxygen gettering layer
Ando, Takashi and Cartier, Eduard A and Chudzik, Michael P and Dasgupta, Aritra and Ho, Herbert L and Kang, DongHun and Krishnan, Rishikesh and Narayanan, Vijay and Rim, Kern
US Patent 9,653,534
Abstract

Method to improve reliability of high-K metal gate stacks
Ando, Takashi and Cartier, Eduard A and Linder, Barry P and Narayanan, Vijay
US Patent 9,634,116
Abstract

High-K spacer for extension-free CMOS devices with high mobility channel materials
Ando, Takashi and Hashemi, Pouya and Narayanan, Vijay and Sun, Yanning
US Patent 9,608,066
Abstract

Scaled cross bar array with undercut electrode
Ando, Takashi and Khater, Marwan H and Kim, Seyoung and Miyazoe, Hiroyuki
US Patent 9,601,546
Abstract

Method of fabricating a semiconductor device including high-K metal gate having reduced threshold voltage variation
Ando, Takashi and Frank, David J
US Patent 9,570,361
Abstract

Fully-depleted SOI MOSFET with U-shaped channel
Ando, Takashi and Dennard, Robert H and Lauer, Isaac and Muralidhar, Ramachandran
US Patent 9,564,500
Abstract

Selective thickening of PFET dielectric
Ando, Takashi and Jagannathan, Hemanth and Linder, Barry P
US Patent 9,570,569
Abstract

Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
Ando, Takashi and Dennard, Robert H and Lauer, Isaac and Muralidhar, Ramachandran and Shahidi, Ghavam G
US Patent 9,627,378
Abstract

Control of O-ingress into gate stack dielectric layer using oxygen permeable layer
Ando, Takashi and Ortolland, Claude and Zhao, Kai
US Patent 9,620,384
Abstract

Gate stack formed with interrupted deposition processes and laser annealing
Ando, Takashi and Dasgupta, Aritra and Gluschenkov, Oleg and Kannan, Balaji and Kwon, Unoh
US Patent 9,613,870
Abstract

Stable work function for narrow-pitch devices
Ando, Takashi and Bajaj, Mohit and Hook, Terence B and Pandey, Rajan K and Sathiyanarayanan, Rajesh
US Patent 9,583,486
Abstract


2016

Field effect transistors having multiple effective work functions
Ando, Takashi and Dai, Min and Kannan, Balaji and Krishnan, Siddarth A and Kwon, Unoh
US Patent 9,484,427
Abstract

Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance
Ando, Takashi and Kannan, Balaji and Narayanan, Vijay
US Patent 9,449,887
Abstract

Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
Ando, Takashi and Narayanan, Vijay
US Patent 9,252,229
Abstract

Replacement metal gate stack for diffusion prevention
Ando, Takashi and Faltermeier, Johnathan E and Fan, Su Chen and Kanakasabapathy, Sivananda K and Injo, OK and Yamashita, Tenko
US Patent 9,312,136
Abstract

Replacement metal gate stack for diffusion prevention
Ando, Takashi and Faltermeier, Johnathan E and Fan, Su Chen and Kanakasabapathy, Sivananda K and Injo, OK and Yamashita, Tenko
US Patent App. 15/068,218
Abstract

Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
Ando, Takashi and Jagannathan, Hemanth and Kannan, Balaji and Krishnan, Siddarth A and Kwon, Unoh and Rajaram, Rekha
US Patent App. 15/058,309
Abstract

Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same
Ando, Takashi and Hashemi, Pouya and Kerber, Pranita and Reznicek, Alexander
US Patent 9,484,412
Abstract

Stacked strained and strain-relaxed hexagonal nanowires
Ando, Takashi and Hashemi, Pouya and Ott, John A and Reznicek, Alexander
US Patent App. 15/249,560
Abstract

Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Ando, Takashi and Bajaj, Mohit and Hook, Terence B and Pandey, Rajan K and Sathiyanarayanan, Rajesh
US Patent App. 15/226,018
Abstract

Method of lateral oxidation of NFET and PFET high-K gate stacks
Ando, Takashi and Dennard, Robert H and Frank, Martin M
US Patent 9,466,492
Abstract

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress
Ando, Takashi and Basker, Veeraraghavan S and Faltermeier, Johnathan E and Jagannathan, Hemanth and Yamashita, Tenko
US Patent 9,472,408
Abstract

Low threshold voltage CMOS device
Ando, Takashi and Choi, Changhwan and Choi, Kisik and Narayanan, Vijay
US Patent 9,263,344
Abstract

Semiconductor device including high-K metal gate having reduced threshold voltage variation
Ando, Takashi and Frank, David J
US Patent 9,425,279
Abstract

Reduction of negative bias temperature instability
Ando, Takashi and Linder, Barry P
US Patent App. 15/068,940
Abstract

High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
Ando, Takashi and Frank, Martin M and Kerber, Pranita and Narayanan, Vijay
US Patent 9,472,553
Abstract

Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability
Ando, Takashi and Cartier, Eduard A and Chan, Kevin K and Narayanan, Vijay
US Patent 9,349,832
Abstract

Methods and structure to form high K metal gate stack with single work-function metal
Ando, Takashi and Kannan, Balaji and Krishnan, Siddarth and Kwon, Unoh and Siddiqui, Shahab
US Patent 9,515,164
Abstract


2015

Method and structure for formation of replacement metal gate field effect transistors
Ando, Takashi and Dasgupta, Aritra and Kannan, Balaji and Kwon, Unoh
US Patent App. 14/721,402
Abstract

Hydroxyl group termination for nucleation of a dielectric metallic oxide
Ando, Takashi and Chudzik, Michael P and Dai, Min and Frank, Martin M and Hilscher, David F and Krishnan, Rishikesh and Linder, Barry P and Ortolland, Claude and Shepard Jr, Joseph F
US Patent App. 14/874,386
Abstract

High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type iii-v semiconductor material and silicon germanium semiconductor material
Ando, Takashi and Frank, Martin M and Kerber, Pranita and Narayanan, Vijay
US Patent App. 14/828,202
Abstract

System on chip material co-integration
Ando, Takashi and Czornomaz, Lukas and Hashemi, Pouya and Reznicek, Alexander
US Patent App. 14/922,251
Abstract

FINFET with U-Shaped Channel
Ando, Takashi and Dennard, Robert H and Lauer, Isaac and Muralidhar, Ramachandran and Shahidi, Ghavam G
US Patent App. 14/788,297
Abstract

Method to improve reliability of replacement gate device
Ando, Takashi and Cartier, Eduard A and Choi, Kisik and Narayanan, Vijay
US Patent 8,999,831
Abstract

Activated thin silicon layers
Ando, Takashi and Frank, Martin M and Narayanan, Vijay and Rozen, John
US Patent App. 14/962,093
Abstract

Concurrently forming nFET and pFET gate dielectric layers
Ando, Takashi and Brodsky, MaryJane and Chudzik, Michael P and Dai, Min and Krishnan, Siddarth A and Shepard Jr, Joseph F and Wang, Yanfeng and Liu, Jinping
US Patent 9,059,315
Abstract

Dual metal-insulator-semiconductor contact structure and formulation method
Ando, Takashi and Niimi, Hiroaki and Yamashita, Tenko
US Patent App. 14/862,894
Abstract

Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures
Ando, Takashi and Cartier, Eduard A and Choi, Kisik and Lai, Wing L and Narayanan, Vijay and Ramachandran, Ravikumar
US Patent 9,099,393
Abstract

Replacement metal gate structure for CMOS device
Ando, Takashi and Choi, Kisik and Samavedam, Srikanth B
US Patent 9,040,404
Abstract

Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET
Ando, Takashi and Choi, Changhwan and Frank, Martin M and Kwon, Unoh and Narayanan, Vijay
US Patent 9,105,745
Abstract


2014

Control of threshold voltages in high-k metal gate stack and structures for CMOS devices
Jagannathan, Hemanth and Ando, Takashi and Narayanan, Vijay
US Patent 8,835,260
Abstract

Devices and methods to optimize materials and properties for replacement metal gate structures
Ando, Takashi and Lavoie, Christian and Narayanan, Vijay
US Patent 8,796,784
Abstract

Structure and method to form input/output devices
Ando, Takashi and Dai, Min and Frank, Martin M and Linder, Barry P and Siddiqui, Shahab
US Patent 8,836,037
Abstract

Interface-free metal gate stack
Ando, Takashi and Choi, Kisik and Copel, Matthew W and Haight, Richard A
US Patent 8,791,004
Abstract

Replacement gate structure for transistor with a high-K gate stack
Ando, Takashi and Cartier, Eduard A and Kwon, Unoh and Narayanan, Vijay
US Patent 8,716,118
Abstract

Reducing the inversion oxide thickness of a high-k stack fabricated on high mobility semiconductor material
Ando, Takashi and Frank, Martin M and Narayanan, Vijay
US Patent 8,853,751
Abstract

Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
Jagannathan, Hemanth and Ando, Takashi and Narayanan, Vijay
US Patent 8,680,629
Abstract

Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
Jagannathan, Hemanth and Ando, Takashi and Narayanan, Vijay
US Patent 8,748,991
Abstract

Gate-last fabrication of quarter-gap MGHK FET
Ando, Takashi and Choi, Kisik and Narayanan, Vijay and Yamashita, Tenko and Wang, Junli
US Patent 8,786,030
Abstract

Multi-layer work function metal replacement gate
Ando, Takashi and Dasgupta, Aritra and Kwon, Unoh and Polvino, Sean M
US Patent 8,647,972
Abstract

FinFET parasitic capacitance reduction using air gap
Ando, Takashi and Chang, Josephine B and Kanakasabapathy, Sivananda K and Kulkarni, Pranita and Standaert, Theodorus E and Yamashita, Tenko
US Patent 8,637,384
Abstract

FinFET parasitic capacitance reduction using air gap
Ando, Takashi and Chang, Josephine B and Kanakasabapathy, Sivananda K and Kulkarni, Pranita and Standaert, Theodorus E and Yamashita, Tenko
US Patent 8,637,930
Abstract


2013

Fabrication of replacement metal gate devices
Ando, Takashi and Charns, Leslie and Cummings, Jason E and Hupka, Lukasz J and Koli, Dinesh R and Konno, Tomohisa and Krishnan, Mahadevaiyer and Lofaro, Michael F and Nalaskowski, Jakub W and Noda, Masahiro and others
US Patent 8,507,383
Abstract

Source-drain extension formation in replacement metal gate transistor device
Ando, Takashi and Bu, Huiming and Divakaruni, Ramachandra and Doris, Bruce B and Lin, Chung-Hsun and Shang, Huiling and Yamashita, Tenko
US Patent 8,592,264
Abstract

Scaled equivalent oxide thickness for field effect transistor devices
Ando, Takashi and Choi, Changhwan and Kwon, Unoh and Narayanan, Vijay
US Patent 8,343,839
Abstract

Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages
Ando, Takashi and Divakaruni, Ramachandra and Kannan, Balaji and Krishnan, Siddarth A and Kumar, Arvind and Kwon, Unoh and Linder, Barry P and Narayanan, Vijay
US Patent App. 13/945,086
Abstract

Replacement metal gate with a conductive metal oxynitride layer
Ando, Takashi and Narayanan, Vijay
US Patent 8,404,530
Abstract

Replacement gate with reduced gate leakage current
Ando, Takashi and Chudzik, Michael P and Krishnan, Rishikesh and Krishnan, Siddarth A and Kwon, Unoh and Wong, Keith Kwong Hon
US Patent 8,581,351
Abstract

Replacement gate devices with barrier metal for simultaneous processing
Ando, Takashi and Chudzik, Michael P and Krishnan, Siddarth A and Kwon, Unoh and Narayanan, Vijay
US Patent 8,420,473
Abstract

FIN Field Effect Transistors Having Multiple Threshold Voltages
Ando, Takashi and Chudzik, Michael P and Kannan, Balaji and Krishnan, Siddarth A and Kwon, Unoh and Narayanan, Vijay
US Patent App. 13/945,095
Abstract

Scavanging metal stack for a high-k gate dielectric
Ando, Takashi and Choi, Changhwan and Frank, Martin M and Narayanan, Vijay
US Patent 8,367,496
Abstract


2012

Structure and method to obtain EOT scaled dielectric stacks
Jagannathan, Hemanth and Ando, Takashi and Edge, Lisa F and Zafar, Sufi and Choi, Changhwan and Jamison, Paul C and Paruchuri, Vamsi K and Narayanan, Vijay
US Patent 8,304,836
Abstract

FET Devices with Oxide Spacers
Ando, Takashi and Kerber, Pranita and Yamashita, Tenko
US Patent App. 13/653,699
Abstract

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device
Ando, Takashi and Cartier, Eduard A and Choi, Changhwan and Duch, Elizabeth A and Doris, Bruce B and Kim, Young-Hee and Narayanan, Vijay and Pan, James and Paruchuri, Vamsi K
US Patent 8,097,500
Abstract


2011

Method of manufacturing semiconductor device includes the step of depositing the capacitor insulating film in a form of a hafnium silicate
Ando, Takashi
US Patent 7,871,883
Abstract

Scavenging metal stack for a high-k gate dielectric
Ando, Takashi and Choi, Changhwan and Frank, Martin M and Narayanan, Vijay
US Patent 7,989,902
Abstract

Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET
Ando, Takashi and Choi, Changhwan and Frank, Martin M and Kwon, Unoh and Narayanan, Vijay
US Patent App. 13/195,316
Abstract


2010

Low dark current image sensors by substrate engineering
Ando, Takashi
US Patent 7,834,412
Abstract

Semiconductor device having dual metal gates and method of manufacture
Kwon, Unoh and Krishnan, Siddarth A and Ando, Takashi and Chudzik, Michael P and Frank, Martin M and Henson, William K and Jha, Rashmi and Liang, Yue and Narayanan, Vijay and Ramachandran, Ravikumar and others
US Patent 7,838,908
Abstract


2008

Method for fabricating semiconductor device
Wang, Wensheng and Ando, Takashi and Hikosaka, Yukinobu
US Patent 7,390,678
Abstract


2007

Scalable high-k dielectric gate stack
Choi, Changhwan and Ando, Takashi and Choi, Kisik and Narayanan, Vijay
US Patent App. 11/928,391
Abstract