Ankur Agrawal  Ankur Agrawal photo       

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Research Staff Member - Mixed Signal Communications IC Design
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash4958

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2016

A 1.8 pJ/bit $16$\backslash$times 16$\backslash$;$\backslash$text $\{$Gb/s$\}$ $ Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
Dickson, Timothy O and Liu, Yong and Agrawal, Ankur and Bulzacchelli, John F and Ainspan, Herschel A and Toprak-Deniz, Zeynep and Parker, Benjamin D and Beakes, Michael P and Meghelli, Mounir and Friedman, Daniel J
IEEE Journal of Solid-State Circuits 51(8), 1744--1755, IEEE, 2016
Abstract

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Rylov, Sergey and Beukema, Troy and Toprak-Deniz, Zeynep and Toifl, Thomas and Liu, Yong and Agrawal, Ankur and Buchmann, Peter and Rylyakov, Alexander and Beakes, Michael and Parker, Benjamin and others
Solid-State Circuits Conference (ISSCC), 2016 IEEE International, pp. 56--57
Abstract

Monolithic Silicon Photonics at 25Gb/s
Orcutt, Jason and Gill, Douglas M and Proesel, Jonathan E and Ellis-Monaghan, John and Horst, Folkert and Barwicz, Tymon and Xiong, Chi and Anderson, Frederick G and Agrawal, Ankur and Martin, Yves and others
Optical Fiber Communication Conference, pp. Th4H--1, 2016
Abstract


2015

Deep learning with limited numerical precision
Gupta, Suyog and Agrawal, Ankur and Gopalakrishnan, Kailash and Narayanan, Pritish
Proceedings of the 32nd International Conference on Machine Learning (ICML-15), pp. 1737--1746, 2015
Abstract

A 1.4 pJ/bit, Power-Scalable 16$\times$ 12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
Dickson, Timothy O and Liu, Yong and Rylov, Sergey V and Agrawal, Ankur and Kim, Seongwon and Hsieh, Ping-Hsuan and Bulzacchelli, John F and Ferriss, Mark and Ainspan, Herschel A and Rylyakov, Alexander and others
IEEE Journal of Solid-State Circuits 50(8), 1917--1931, IEEE, 2015
Abstract


2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOICMOS
A. Agrawal, J.F. Bulzacchelli, T.O. Dickson, Y. Liu, J.A. Tierno, D.J. Friedman
Solid-State Circuits, IEEE Journal of 47(12), 3220-3231, IEEE, 2012

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, D. Friedman
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 134--136


2011

Area efficient phase calibration of a 1.6 GHz multiphase DLL
A. Agrawal, P.K. Hanumolu, G.Y. Wei
Custom Integrated Circuits Conference (CICC), 2011 IEEE, pp. 1--4


2010



2009

An 8$, times, $5 Gb/s Parallel Receiver With Collaborative Timing Recovery
A. Agrawal, A. Liu, P.K. Hanumolu, G.Y. Wei
Solid-State Circuits, IEEE Journal of 44(11), 3120--3130, IEEE, 2009


2008

A 8$\times$ 5 Gb/s source-synchronous receiver with clock generator phase error correction
A. Agrawal, P.K. Hanumolu, G.Y. Wei
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, pp. 459--462