Dureseti (Chidu) Chidambarrao  Dureseti  (Chidu) Chidambarrao photo       

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STSM-DfM; Master Inventor

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Professional Associations

Professional Associations:  Electrochemical Society (ECS)  |  IBM Academy of Technology  |  IBM Industry Academy  |  IEEE   |  IEEE Electron Devices Society (EDS)  |  IEEE Member  |  Materials Research Society (MRS)


2016

Correcting for stress induced pattern shifts in semiconductor manufacturing
Chidambarrao, Dureseti and Culp, James A and Parries, Paul C and Stobert, Ian P
US Patent 9,311,443
Abstract

Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects
Banerjee, Shayak and Chidambarrao, Dureseti and Shao, Dongbing
US Patent 9,342,648
Abstract


2015

Circuit technique to electrically characterize block mask shifts
Acar, Emrah and Bansal, Aditya and Chidambarrao, Dureseti and Pang, Liang-Teck and Singhee, Amith
US Patent 8,969,104
Abstract


2014

MOS having a sic/sige alloy stack
Chidambarrao, Dureseti and Greene, Brian J and Liang, Yue and Yu, Xiaojun
US Patent 8,835,234
Abstract

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor
Liang, Yue and Chidambarrao, Dureseti and Greene, Brian J and Henson, William K and Kwon, Unoh and Narasimha, Shreesh and Yu, Xiaojun
US Patent 8,803,243
Abstract

Stress-generating structure for semiconductor-on-insulator devices
Zhu, Huilong and Greene, Brian J and Chidambarrao, Dureseti and Freeman, Gregory G
US Patent 8,629,501
Abstract

Silicon nanotube MOSFET
Tekleab, Daniel and Tran, Hung H and Sleight, Jeffrey W and Chidambarrao, Dureseti
US Patent 8,871,576
Abstract


2013

Field effect transistor having multiple conduction states
Chidambarrao, Dureseti and Onsongo, David M and Hanson, David R
US Patent 8,405,165
Abstract

Selective partial gate stack for improved device isolation
Yu, Xiaojun and Chidambarrao, Dureseti and Greene, Brian J and Liang, Yue
US Patent 8,466,496
Abstract

Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
Banerjee, Shayak and Chidambarrao, Dureseti and Culp, James A and Elakkumanan, Praveen and Mukhopadhyay, Saibal
US Patent 8,418,087
Abstract

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same
Chidambarrao, Dureseti and Fang, Sunfei and Liang, Yue and Yu, Xiaojun and Yuan, Jun
US Patent 8,445,974
Abstract

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers
Chidambarrao, Dureseti and Muralidhar, Ramachandran and Oldiges, Philip J and Ontalus, Viorel
US Patent 8,541,814
Abstract

Multiple orientation nanowires with gate stack stressors
Chidambarrao, Dureseti and Liu, Xiao Hu and Sekaric, Lidija
US Patent 8,368,125
Abstract

Multiple Orientation Nanowires with Gate Stack Sensors
Chidambarrao, Dureseti and Liu, Xiao Hu and Sekaric, Lidija
US Patent 8,367,492
Abstract

Circuit analysis using transverse buckets
Chidambarrao, Dureseti and Williams, Richard Q
US Patent 8,453,100
Abstract

CMOS having a SiC/SiGe alloy stack
Chidambarrao, Dureseti and Greene, Brian J and Liang, Yue and Yu, Xiaojun
US Patent 8,476,706
Abstract


2012

Nanowire devices for enhancing mobility through stress engineering
Chidambarrao, Dureseti and Liu, Xiao H and Sekaric, Lidija
US Patent 8,237,150
Abstract

IC having viabar interconnection and related method
Chidambarrao, Dureseti and Greco, Stephen E and Low, Kia S
US Patent 8,299,622
Abstract

Methodology for improving device performance prediction from effects of active area corner rounding
Chidambarrao, Dureseti and Davidson, Gerald M and Hyde, Paul A and McCullen, Judith H and Narasimha, Shreesh
US Patent 8,296,691
Abstract

Silicon device on Si: C SOI and SiGe and method of manufacture
Chidambarrao, Dureseti and Dokumaci, Omer H and Gluschenkov, Oleg G
US Patent 8,119,472
Abstract

Formation of improved SOI substrates using bulk semiconductor wafers
Henson, William K and Chidambarrao, Dureseti and Rim, Kern and Wann, Hsingjen and Ng, Hung Y
US Patent 8,268,698
Abstract

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
Zhu, Huilong and Greene, Brian J and Chidambarrao, Dureseti and Freeman, Gregory G
US Patent 8,115,254
Abstract

Film wrapped NFET nanowire
Chidambarrao, Dureseti and Sekaric, Lidija
US Patent 8,232,165
Abstract

Methods and system for analysis and management of parametric yield
Culp, James A and Chang, Paul and Chidambarrao, Dureseti and Elakkumanan, Praveen and Hibbeler, Jason and Mocuta, Anda C
US Patent 8,239,790
Abstract

Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Liu, Yaocheng and Chidambarrao, Dureseti and Gluschenkov, Oleg and Holt, Judson R and Mo, Renee T and Rim, Kern
US Patent 8,217,423
Abstract


2011

Compact model methodology for PC landing pad lithographic rounding impact on device performance
Chidambarrao, Dureseti and Davidson, Gerald M and Hyde, Paul A and McCullen, Judith H and Narasimha, Shreesh
US Patent 7,979,815
Abstract

Nanostructure For Changing Electric Mobility
Chidambarrao, Dureseti and Gunawan, Oki and Liu, Xiao Hu and Majumdar, Amlan and Sekaric, Lidija and Sleight, Jeffrey W
US Patent App. 12/505,603
Abstract

Intersect area based ground rule for semiconductor design
Avanessian, Albrik and Bonges III, Henry A and Chidambarrao, Dureseti and Greco, Stephen E and Kemerer, Douglas W and Wagner, Tina
US Patent 7,941,780
Abstract

Structurally stabilized semiconductor nanowire
Chidambarrao, Dureseti and Sekaric, Lidija
US Patent 8,013,324
Abstract

Hybrid orientation scheme for standard orthogonal circuits
Chidambarrao, Dureseti
US Patent 8,053,844
Abstract

Methods and system for analysis and management of parametric yield
Culp, James A and Chang, Paul and Chidambarrao, Dureseti and Elakkumanan, Praveen and Hibbeler, Jason and Mocuta, Anda C
US Patent 8,042,070
Abstract

Electrical fuse having a fully silicided fuselink and enhanced flux divergence
Chidambarrao, Dureseti and Henson, William K and Kim, Deok-kee and Kothandaraman, Chandrasekharan
US Patent 7,943,493
Abstract

Asymmetric semiconductor devices and method of fabricating
Yuan, Jun and Chidambarrao, Dureseti and Fang, Sunfei and Liang, Yue and Yin, Haizhou and Yu, Xiaojun
US Patent 7,999,332
Abstract

Semiconductor nanowires having mobility-optimized orientations
Sekaric, Lidija and Barwicz, Tymon and Chidambarrao, Dureseti
US Patent 7,943,530
Abstract

System and methodology for determining layout-dependent effects in ULSI simulation
Chidambarrao, Dureseti and Li, Tong and Williams, Richard Q and Winston, David W
US Patent 8,037,433
Abstract

Gate electrode stress control for finFET performance enhancement description
Chidambarrao, Dureseti
US Patent 7,960,801
Abstract

eFuse with partial SiGe layer and design structure therefor
Kothandaraman, Chandrasekharan and Kim, Deok-kee and Chidambarrao, Dureseti and Henson, William K
US Patent 7,960,809
Abstract

eFuse containing SiGe stack
Kim, Deok-kee and Chidambarrao, Dureseti and Henson, William K and Kothandaraman, Chandrasekharan
US Patent 8,004,059
Abstract

Structure and method for mosfet with reduced extension resistance
Chidambarrao, Dureseti and Radens, Carl
US Patent 7,960,237
Abstract

Semiconductor nanowire with built-in stress
Sekaric, Lidija and Chidambarrao, Dureseti and Liu, Xiao H
US Patent 7,902,541
Abstract

Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
Chidambarrao, Dureseti and Henson, William K and Liu, Yaocheng
US Patent 7,888,197
Abstract

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
Chen, Huajie and Chidambarrao, Dureseti and Holt, Judson R and Ouyang, Qiqing C and Panda, Siddhartha
US Patent 7,863,197
Abstract


2010

Multiple conduction state devices having differently stressed liners
Chidambarrao, Dureseti and Onsongo, David M
US Patent 7,768,041
Abstract

Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
Chakravarti, Ashima B and Chidambarrao, Dureseti and Holt, Judson R and Liu, Yaocheng and Rim, Kern
US Patent 7,838,932
Abstract

Device having enhanced stress state and related methods
Chidambarrao, Dureseti and Li, Ying and Malik, Rajeev and Narasimha, Shreesh and Yang, Haining and Zhu, Huilong
US Patent 7,732,270
Abstract

Automated optimization of device structure during circuit design stage
Chidambarrao, Dureseti and Hibbeler, Jason and Williams, Richard Q
US Patent 7,818,692
Abstract

WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST
Chidambarrao, Dureseti and Davidson, Gerald M and Hyde, Paul A and Mccullen, Judith H and Narasimha, Shreesh

Abstract

Reduction of boron diffusivity in pFETs
Buehrer, Frederick William and Chidambarrao, Dureseti and Doris, Bruce B and Huang, Hsiang-Jen and Yang, Haining
US Patent 7,737,014
Abstract

Sidewall semiconductor transistors
Zhu, Huilong and Clevenger, Lawrence A and Dokumaci, Omer H and Kumar, Kaushik A and Radens, Carl J and Chidambarrao, Dureseti
US Patent 7,696,025
Abstract

Method for fabricating a semiconductor structure
Zhu, Huilong and Clevenger, Lawrence A and Dokumaci, Omer H and Gluschenkov, Oleg and Kumar, Kaushik A and Radens, Carl J and Chidambarrao, Dureseti
US Patent 7,732,288
Abstract

Semiconductor structure for low parasitic gate capacitance
Henson, William K and Chang, Paul Chung-Muh and Chidambarrao, Dureseti and Donaton, Ricardo A and Liu, Yaocheng and Narasimha, Shreesh and Tessier, Amanda L
US Patent 7,709,910
Abstract

Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof
Cheng, Changguo and Chidambarrao, Dureseti and Greene, Brian Joseph and Mandelman, Jack A and Rim, Kern
US Patent 7,812,397
Abstract

Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
Chidambarrao, Dureseti and Liu, Yaocheng and Henson, William K
US Patent 7,675,118
Abstract

Creating increased mobility in a bipolar device
Chidambarrao, Dureseti and Freeman, Gregory G and Khater, Marwan H
US Patent 7,741,186
Abstract

Semiconductor device structure having low and high performance devices of same conductive type on same substrate
Arnold, John C and Chidambarrao, Dureseti and Li, Ying and Malik, Rajeev and Narasimha, Shreesh and Panda, Siddhartha and Tessier, Brian L and Wise, Richard
US Patent 7,776,695
Abstract

CA resistance variability prediction methodology
Chidambarrao, Dureseti and Heng, Fook-Luen and Lavin, Mark A and Lee, Jin-Fuw and Singh, Rama N and Tsai, Roger Y
US Patent 7,831,941
Abstract

Transistor with dielectric stressor element fully underlying the active semiconductor region
Chidambarrao, Dureseti and Greene, Brian J and Rim, Kern
US Patent 7,659,581
Abstract

Transistor with dielectric stressor elements
Chidambarrao, Dureseti and Greene, Brian J and Rim, Kern
US Patent 7,759,739
Abstract

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same
Belyansky, Michael P and Chidambarrao, Dureseti and Clevenger, Lawrence A and Kumar, Kaushik A and Radens, Carl
US Patent 7,659,160
Abstract

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same
Belyansky, Michael P and Chidambarrao, Dureseti and Clevenger, Lawrence A and Kumar, Kaushik A and Radens, Carl
US Patent 7,648,871
Abstract

Stressed field effect transistors on hybrid orientation substrate
Chidambarrao, Dureseti and Holt, Judson R and Ieong, Meikei and Ouyang, Qiqing C and Panda, Siddhartha
US Patent 7,687,829
Abstract

Gate electrode stress control for finFET performance enhancement
Chidambarrao, Dureseti
US Patent 7,655,511
Abstract

Method and structure for improving device performance variation in dual stress liner technology
Chidambarrao, Dureseti and Greene, Brian J
US Patent 7,843,024
Abstract

Semiconductor device stress modeling methodology
Chidambarrao, Dureseti and Williams, Richard Q
US Patent 7,761,278
Abstract

Semiconductor device structures incorporating voids and methods of fabricating such structures
Chidambarrao, Dureseti and Donaton, Ricardo Alves and Mandelman, Jack Allan
US Patent 7,691,712
Abstract

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
Chen, Huajie and Chidambarrao, Dureseti and Schepis, Dominic J and Utomo, Henry K
US Patent 7,781,800
Abstract

High performance strained silicon FinFETs device and method for forming same
Bedell, Stephen W and Chan, Kevin K and Chidambarrao, Dureseti and Christianson, Silke H and Chu, Jack O and Domenicucci, Anthony G and Lee, Kam-Leung and Mocuta, Anda C and Ott, John A and Ouyang, Qiqing C and others
US Patent 7,705,345
Abstract

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
Chidambarrao, Dureseti and Mocuta, Anda C and Mocuta, Dan M and Radens, Carl
US Patent 7,691,698
Abstract

Vertical fin-fet mos devices
Chidambarrao, Dureseti and Beintner, Jochen and Divakaruni, Ramachandra
US Patent 7,683,428
Abstract

High performance stress-enhance MOSFET and method of manufacture
Chidambarrao, Dureseti and Donaton, Ricardo A and Henson, William K and Rim, Kern
US Patent 7,791,144
Abstract


2009

Structure and method for fabrication of deep junction silicon-on-insulator transistors
Chidambarrao, Dureseti and Greene, Brian J and Ellis-Monaghan, John J
US Patent 7,534,667
Abstract

After gate fabrication of field effect transistor having tensile and compressive regions
Chidambarrao, Dureseti and Henson, William K and Liu, Yaocheng
US Patent 7,485,519
Abstract

CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type
Chidambarrao, Dureseti
US Patent 7,573,104
Abstract

Rotational shear stress for charge carrier mobility modification
Chidambarrao, Dureseti
US Patent 7,504,697
Abstract

Mobility enhancement in SiGe heterojunction bipolar transistors
Adam, Thomas N and Chidambarrao, Dureseti
US Patent 7,544,577
Abstract

Stressed SOI FET having tensile and compressive device regions
Chidambarrao, Dureseti and Henson, William K and Liu, Yaocheng
US Patent 7,632,724
Abstract

Electrical fuse with a thinned fuselink middle portion
Chidambarrao, Dureseti and Henson, William K and Kim, Deok-kee and Kothandaraman, Chandrasekharan
US Patent 7,550,323
Abstract

Strained dislocation-free channels for CMOS and method of manufacture
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 7,495,291
Abstract

Silicon/silcion germaninum/silicon body device with embedded carbon dopant
Mocuta, Anda C and Chidambarrao, Dureseti and Donaton, Ricardo A and Onsongo, David M and Rim, Kern
US Patent 7,560,326
Abstract

Curved FINFETs
Chidambarrao, Dureseti and Narasimha, Shreesh and Nowak, Edward J and Pekarik, John J and Sleight, Jeffrey W and Williams, Richard Q
US Patent 7,538,391
Abstract


2008

Low resistance contact semiconductor device structure
Chidambarrao, Dureseti and Henson, William K
US Patent 7,439,123
Abstract

Device having dual etch stop liner and reformed silicide layer and related methods
Chidambarrao, Dureseti and Li, Ying and Malik, Rajeev and Narasimha, Shreesh
US Patent 7,446,062
Abstract

Device having dual etch stop liner and protective layer
Chidambarrao, Dureseti and Li, Ying and Malik, Rajeev and Narasimha, Shreesh
US Patent 7,446,395
Abstract

Strained silicon on a SiGe on SOI substrate
Cheng, Kangguo and Chidambarrao, Dureseti
US Patent 7,468,538
Abstract

Method for reduced N+ diffusion in strained Si on SiGe substrate
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 7,410,846
Abstract

Field effect transistors with dielectric source drain halo regions and reduced miller capacitance
Belyansky, Michael P and Chidambarrao, Dureseti and Gluschenkov, Oleg
US Patent 7,342,266
Abstract

Semiconductor devices having torsional stresses
Williams, Richard Q and Chidambarrao, Dureseti and Ellis-Monaghan, John J and Narasimha, Shreesh and Nowak, Edward J and Pekarik, John J
US Patent 7,462,916
Abstract

Embedded stressed nitride liners for CMOS performance improvement
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 7,361,973
Abstract

Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
Chidambarrao, Dureseti and Jordan, Donald L and McCullen, Judith H and Onsongo, David M and Wagner, Tina and Williams, Richard Q
US Patent 7,337,420
Abstract

Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
Chidambarrao, Dureseti and Greene, Brian J
US Patent 7,358,551
Abstract

Strained finFET CMOS device structures
Doris, Bruce B and Chidambarrao, Dureseti and Ieong, Meikei and Mandelman, Jack A
US Patent 7,388,259
Abstract


2007

Method of making strained channel CMOS transistors having lattice-mismatched epitaxial
Chen, Huajie and Chidambarrao, Dureseti and Dokumaci, Omer O and Yang, Haining S
US Patent 7,297,583
Abstract

MOSFET with high angle sidewall gate and contacts for reduced miller capacitance
Chidambarrao, Dureseti and Clevenger, Lawrence A and Dokumaci, Omer H and Kumar, Kaushik A and Zhu, Huilong
US Patent 7,224,021
Abstract

Enhanced PFET using shear stress
Chidambarrao, Dureseti
US Patent 7,274,084
Abstract

Method and structure for semiconductor devices with silicon-germanium deposits
Adam, Thomas N and Black, Linda and Chen, Huajie and Chidambarrao, Dureseti and Davis, Robert E and Holt, Judson R and Knarr, Randolph F and Lavoie, Christian and Purtell, Robert J and Schepis, Dominic J and others
US Patent App. 11/955,488
Abstract

Electrical fuse with enhanced programming current divergence
Chidambarrao, Dureseti and Henson, William K and Kim, Deok-kee and Kothandaraman, Chandrasekharan
US Patent App. 11/835,846
Abstract

Design Structure Incorporating Semiconductor Device Structures with Voids
Chidambarrao, Dureseti and Donaton, Ricardo and Mandelman, Jack
US Patent App. 11/875,986
Abstract

Dual stressed SOI substrates
Chidambarrao, Dureseti and Dokumaci, Omer H and Doris, Bruce B and Gluschenkov, Oleg and Zhu, Huilong
US Patent 7,312,134
Abstract

Dual stressed SOI substrates
Chidambarrao, Dureseti and Doris, Bruce B and Gluschenkov, Oleg and Dokumaci, Omer H and Zhu, Huilong
US Patent 7,262,087
Abstract

Method for forming dual etch stop liner and protective layer in a semiconductor device
Chidambarrao, Dureseti and Li, Ying and Malik, Rajeev and Narasimha, Shreesh
US Patent 7,306,983
Abstract

Transistor having dielectric stressor elements for applying in-plane shear stress
Chidambarrao, Dureseti and Green, Brian J and Rim, Kern
US Patent 7,221,024
Abstract

Strained Si on multiple materials for bulk or SOI substrates
Chidambarrao, Dureseti and Dokumaci, Omer H and Gluschenkov, Oleg G and Zhu, Huilong
US Patent 7,223,994
Abstract

Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
Hanson, David R and Chidambarrao, Dureseti and Fredeman, Gregory J and Onsongo, David M
US Patent 7,242,239
Abstract

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
Chen, Huajie and Chidambarrao, Dureseti and Gluschenkov, Oleg G and Steegen, An L and Yang, Haining S
US Patent 7,291,528
Abstract

Trench capacitor DRAM cell using buried oxide as array top oxide
Chidambarrao, Dureseti and Divakaruni, Ramachandra and Kim, Deok-kee
US Patent 7,195,972
Abstract

Stress engineering using dual pad nitride with selective SOI device architecture
Chidambarrao, Dureseti and Henson, William K and Rim, Kern and Wille, William C
US Patent 7,202,513
Abstract

High performance CMOS device structures and method of manufacture
Doris, Bruce B and Chidambarrao, Dureseti and Ku, Suk Hoon
US Patent 7,279,746
Abstract

N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers
Chidambarrao, Dureseti and Leobandung, Effendi and Mocuta, Anda C and Mocuta, Dan M and Onsongo, David M and Radens, Carl J
US Patent App. 11/307,224
Abstract

Crystallographic recess etch for embedded semiconductor region
Dyer, Thomas W and Chidambarrao, Dureseti
US Patent App. 11/693,792
Abstract

High performance stress-enhanced MOSFETs using Si: C and SiGe epitaxial source/drain and method of manufacture
Chen, Huajie and Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 7,303,949
Abstract

In situ doped embedded sige extension and source/drain for enhanced PFET performance
Chen, Huajie and Chidambarrao, Dureseti and Panda, Siddhartha and Oh, Sang-Hyun and Utomo, Henry K and Rausch, Werner A
US Patent 7,176,481
Abstract

Silicon device on Si: C-OI and SGOI and method of manufacture
Chidambarrao, Dureseti and Dokumaci, Omer H and Gluschenkov, Oleg G
US Patent 7,247,534
Abstract

Structure of vertical strained silicon devices
Cheng, Kangguo and Chidambarrao, Dureseti and Divakaruni, Rama and Gluschenkov, Oleg G
US Patent 7,170,126
Abstract

Strained finFETs and method of manufacture
Chidambarrao, Dureseti and Dokumaci, Omer H and Gluschenkov, Oleg G
US Patent 7,198,995
Abstract


2006

Semiconductor structure including multiple stressed layers
Henson, William K and Chidambarrao, Dureseti and Liu, Yaocheng
US Patent App. 11/467,721
Abstract

Sense amplifier including multiple conduction state field effect transistor
Hanson, David R and Onsongo, David M and Chidambarrao, Dureseti
US Patent 7,123,529
Abstract

Automated optimization of vlsi layouts for regularity
Chidambarrao, Dureseti and Culp, James A and Hibbeler, Jason D
US Patent App. 11/614,260
Abstract

Stressed semiconductor device structures having granular semiconductor material
Doris, Bruce B and Belyansky, Michael P and Boyd, Diane C and Chidambarrao, Dureseti and Gluschenkov, Oleg
US Patent 7,122,849
Abstract

Optimized deep source/drain junctions with thin poly gate in a field effect transistor
Chidambarrao, Dureseti and Liu, Yaocheng and Rim, Kern
US Patent App. 11/420,053
Abstract

Method of manufacturing a strained silicon on a SiGe on SOI substrate
Cheng, Kangguo and Chidambarrao, Dureseti
US Patent 7,029,964
Abstract

NFETs using gate induced stress modulation
Chidambarrao, Dureseti and Dokumaci, Omer H and Gluschenkov, Oleg G
US Patent 7,144,767
Abstract

Gate controlled floating well vertical MOSFET
Chen, Xiangdong and Chidambarrao, Dureseti and Wang, Geng
US Patent 7,102,914
Abstract

Out of the box vertical transistor for eDRAM on SOI
Adkisson, James W and Bronner, Gary B and Chidambarrao, Dureseti and Divakaruni, Ramachandra and Radens, Carl J
US Patent 7,129,130
Abstract

Dynamic threshold voltage MOSFET on SOI
Chen, Xiangdong and Chidambarrao, Dureseti and Wang, Geng
US Patent 7,045,873
Abstract

Out of the box vertical transistor for eDRAM on SOI
Adkisson, James W and Bronner, Gary B and Chidambarrao, Dureseti and Divakaruni, Ramachandra and Radens, Carl J
US Patent 7,009,237
Abstract

Bipolar transistor with extrinsic stress layer
Chidambarrao, Dureseti and Freeman, Gregory G and Khater, Marwan H
US Patent 7,102,205
Abstract

Method of manufacturing strained dislocation-free channels for CMOS
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 7,037,770
Abstract

Structure and method for making strained channel field effect transistor using sacrificial spacer
Chen, Huajie and Chidambarrao, Dureseti and Oh, Sang-Hyun and Panda, Siddhartha and Rausch, Werner A and Sato, Tsutomu and Utomo, Henry K
US Patent 7,135,724
Abstract

MOSFET structure with high mechanical stress in the channel
Chen, Xiangdong and Chidambarrao, Dureseti and Gluschenkov, Oleg and Greene, Brian and Rim, Kern and Yang, Haining S
US Patent 7,002,209
Abstract

Pull-back method of forming fins in FinFets
Beintner, Jochen C and Chidambarrao, Dureseti and Li, Yujun and Settlemyer Jr, Kenneth T
US Patent 7,018,551
Abstract

Laser surface annealing of antimony doped amorphized semiconductor region
Chidambarrao, Dureseti and Jain, Sameer and Henson, William and Rim, Kern
US Patent App. 11/308,108
Abstract

Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
Chidambarrao, Dureseti and Dokumaci, Omer
US Patent 7,060,539
Abstract


2005

Structure and method for ultra-small grain size polysilicon
Beintner, Jochen and Chidambarrao, Dureseti
US Patent 6,967,384
Abstract

Structure and method of vertical transistor DRAM cell having a low leakage buried strap
Chidambarrao, Dureseti and Mandelman, Jack Allan and Radens, Carl John
US Patent 6,979,851
Abstract

Strained silicon on relaxed sige film with uniform misfit dislocation density
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 6,872,641
Abstract

Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling
Wang, Geng and Mcstay, Kevin and Weybright, Mary Elizabeth and Li, Yujun and Chidambarrao, Dureseti
US Patent 6,930,004
Abstract

Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain
Cheng, Kangguo and Chidambarrao, Dureseti and Greene, Brian and Mandelman, Jack and Rim, Kern
US Patent App. 11/162,959
Abstract

Trench capacitors with reduced polysilicon stress
Chidambarrao, Dureseti and Jammy, Rajarao and Mandelman, Jack A
US Patent 6,872,620
Abstract

Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current
Belyansky, Michael and Chidambarrao, Dureseti and Dokumaci, Omer and Gluschenkov, Oleg
US Patent App. 11/162,778
Abstract

High performance logic and high density embedded dram with borderless contact and antispacer
Chidambarrao, Dureseti and Dokumaci, Omer H and Doris, Bruce Bennett and Gluschenkov, Oleg and Jammy, Rajarao and Mandelman, Jack Allen
US Patent 6,873,010
Abstract

Low modulus spacers for channel stress enhancement
Chidambarrao, Dureseti and Utomo, Henry
US Patent App. 11/163,871
Abstract

Structure and method to enhance stress in a channel of cmos devices using a thin gate
Zhu, Huilong and Yang, Haining and Gluschenkov, Oleg and Chidambarrao, Dureseti and Luo, Zhijiong
US Patent App. 10/905,710
Abstract

Field effect transistor with stressed channel and method for making same
Doris, Bruce B and Chidambarrao, Dureseti and Baie, Xavier and Mandelman, Jack A and Sadana, Devendra K and Schepis, Dominic J
US Patent 6,884,667
Abstract

Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
Chen, Huajie and Chidambarrao, Dureseti and Dokumaci, Omer O and Yang, Haining S
US Patent 6,906,360
Abstract

Silicide proximity structures for CMOS device performance improvements
Chidambarrao, Dureseti and Dokumaci, Omer H and Rengarajan, Rajesh and Steegen, An L
US Patent 6,869,866
Abstract

Method and structure for improved MOSFETs using poly/silicide gate height control
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 6,890,808
Abstract

MOSFET performance improvement using deformation in SOI structure
Chidambarrao, Dureseti and Dokumaci, Omer H
US Patent 6,887,751
Abstract

Channel MOSFET with strained silicon channel on strained SiGe
Chen, Xiangdong and Chidambarrao, Dureseti and Wang, Geng and Zhu, Huilong
US Patent 6,972,461
Abstract

Strained silicon NMOS devices with embedded source/drain
Chidambarrao, Dureseti and Leobandung, Effendi and Mocuta, Anda C and Yang, Haining S and Zhu, Huilong
US Patent 6,881,635
Abstract

Isolation structures for imposing stress patterns
Chidambarrao, Dureseti and Dokumaci, Omer H and Doris, Bruce B and Mandelman, Jack A
US Patent 6,974,981
Abstract

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
Chen, Huajie and Chidambarrao, Dureseti and Gluschenkov, Oleg G and Steegen, An L and Yang, Haining S
US Patent 6,891,192
Abstract

Structure and method to improve channel mobility by gate electrode stress modification
Belyansky, Michael P and Chidambarrao, Dureseti and Dokumaci, Omer H and Doris, Bruce B and Gluschenkov, Oleg
US Patent 6,977,194
Abstract


2004

Lowered Source/Drain Transistors
Zhu, Huilong and Clevenger, Lawrence and Dokumaci, Omer and Gluschenkov, Oleg and Kumar, Kaushik and Radens, Carl and Chidambarrao, Dureseti
US Patent App. 10/904,660
Abstract

Method for preventing strap-to-strap punch through in vertical DRAMs
Akatsu, Hiroyuki and Chidambarrao, Dureseti and Divakaruni, Ramachandra and Mandelman, Jack and Radens, Carl J
US Patent 6,724,031
Abstract

CMOS performance enhancement using localized voids and extended defects
Dokumachi, Omer H and Chidambarrao, Dureseti and Hegde, Suryanarayan G
US Patent 6,803,270
Abstract

Vertical DRAM punchthrough stop self-aligned to storage trench
Mandelman, Jack A and Chidambarrao, Dureseti and Divakaruni, Ramachandra
US Patent 6,777,737
Abstract

Buried strap with limited outdiffusion and vertical transistor DRAM
Chidambarrao, Dureseti and Divakaruni, Ramachandra and Mandelman, Jack A and Van Roijen, Raymond
US Patent 6,703,274
Abstract

Vertical DRAM punchthrough stop self-aligned to storage trench
Mandelman, Jack A and Chidambarrao, Dureseti and Divakaruni, Ramachandra
US Patent 6,833,305
Abstract

Vertical MOSFET with horizontally graded channel doping
Chidambarrao, Dureseti and Lee, Kil-Ho and Mandelman, Jack A and McStay, Kevin and Rengarajan, Rajesh
US Patent 6,740,920
Abstract

Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation
Chidambarrao, Dureseti and Mandelman, Jack A and Radens, Carl J
US Patent 6,707,095
Abstract

Stress inducing spacers
Chidambarrao, Dureseti and Dokumaci, Omer H and Doris, Bruce B and Mandelman, Jack A and Baie, Xavier
US Patent 6,825,529
Abstract

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
Doris, Bruce B and Chidambarrao, Dureseti and Baie, Xavier and Mandelman, Jack A and Sadana, Devendra K and Schepis, Dominic J
US Patent 6,717,216
Abstract


2003

Vertical MOSFET with asymmetrically graded channel doping
Chidambarrao, Dureseti and Divakaruni, Ramachandra and Mandelman, Jack A and McStay, Kevin
US Patent 6,573,561
Abstract

Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell
Mandelman, Jack A and Chidambarrao, Dureseti
US Patent 6,534,824
Abstract

Reduction of polysilicon stress in trench capacitors
Chidambarrao, Dureseti and Jammy, Rajarao and Mandelman, Jack A
US Patent 6,653,678
Abstract


2002

Structure and method of providing reduced programming voltage antifuse
Chidambarrao, Dureseti and Frey, Ulrich and Hegde, Suryanarayan and Tonti, William
US Patent App. 10/243,540
Abstract

Process for producing metal interconnections and product produced thereby
Chidambarrao, Dureseti and Filippi, Ronald G and Rosenberg, Robert and Shaw, Thomas M and Sullivan, Timothy D and Wachnik, Richard A
US Patent 6,417,572
Abstract


2001

Reducing metal voids during BEOL metallization
Chidambarrao, Dureseti and others
US Patent 6,177,286
Abstract

Electrically blowable fuse with reduced cross-sectional area
Arndt, Kenneth C and Chidambarrao, Dureseti and Hsu, Louis L and Mandelman, Jack A and Radens, Carl
US Patent 6,222,244
Abstract


1998

Integrated ULSI heatsink
Tonti, William R and Mandelman, Jack A and Zalesinski, Jerzy M and Furukawa, Toshiharu and Nguyen, Son V and Chidambarrao, Dureseti
US Patent 5,729,052
Abstract

Method of manufacturing an integrated ULSI heatsink
Tonti, William R and Mandelman, Jack A and Zalesinski, Jerzy M and Furukawa, Toshiharu and Nguyen, Son V and Chidambarrao, Dureseti
US Patent 5,773,362
Abstract


1995

Method to reduce stress from trench structure on SOI wafer
Chidambarrao, Dureseti and Hsu, Louis L and Mis, J Daniel and Peng, James P
US Patent 5,470,781
Abstract