Mihir Choudhury  Mihir Choudhury photo       

contact information

Research Staff member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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2015

Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs
Subhendu Roy, Mihir Choudhury, Ruchir Puri, David Pan
Asia and South Pacific Design Automation Conference (ASP-DAC), 2015


2014

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis
Mahmoud Elbayoumi, Mihir Choudhury, Victor Kravets, Andrew Sullivan, Michael Hsiao, Mustafa Elnainay
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, pp. 1--6, 2014


2013

Low Cost Concurrent Error Masking Using Approximate Logic Circuits
Mihir R Choudhury, Kartik Mohanram
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 32(8), 1163--1176, IEEE, 2013

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Subhendu Roy, Mihir Choudhury, Ruchir Puri, David Z Pan
Proceedings of the 50th Annual Design Automation Conference, pp. 48, 2013


2012

Time-borrowing circuit designs and hardware prototyping for timing error resilience
M Choudhury, Vikas Chandra, R Aitken, Kartik Mohanram
IEEE, 2012


2011

Approximate logic circuits: Theory and applications
Mihir Choudhury
Ph.D. Thesis, 2011

Reliability-driven don't care assignment for logic synthesis
A Zukoski, MR Choudhury, K Mohanram
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2011, pp. 1--6

Graphene nanoribbon FETs: Technology exploration for performance and reliability
Mihir R Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
Nanotechnology, IEEE Transactions on 10(4), 727--736, IEEE, 2011


2010

Dominant critical gate identification for power and yield optimization in logic circuits
Mihir Choudhury, Masoud Rostami, Kartik Mohanram
Proceedings of the 20th symposium on Great lakes symposium on VLSI, pp. 173--178, 2010

Bi-decomposition of large Boolean functions using blocking edge graphs
Mihir Choudhury, Kartik Mohanram
Proceedings of the International Conference on Computer-Aided Design, pp. 586--591, 2010

TIMBER: Time borrowing and error relaying for online timing error resilience
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, Robert Aitken
Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1554--1559, 2010

Analytical model for TDDB-based performance degradation in combinational logic
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, Robert Aitken
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2010, pp. 423--428


2009

Timing-driven optimization using lookahead logic circuits
Mihir Choudhury, Kartik Mohanram
Design Automation Conference, 2009. DAC'09. 46th ACM/IEEE, pp. 390--395

Masking timing errors on speed-paths in logic circuits
Mihir R Choudhury, Kartik Mohanram
Design, Automation \& Test in Europe Conference \& Exhibition, 2009. DATE'09., pp. 87--92

Soft error rate reduction using circuit optimization and transient filter insertion
Mihir R Choudhury, Quming Zhou, Kartik Mohanram
Journal of Electronic Testing 25(2), 197--207, Springer, 2009

Reliability analysis of logic circuits
Mihir R Choudhury, Kartik Mohanram
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 28(3), 392--405, IEEE, 2009


2008

Logic Design for Reliability
Mihir Choudhury
ProQuest, 2008

Analytical theory of graphene nanoribbon transistors
Pei Zhao, Mihir Choudhury, Kartik Mohanram, Jing Guo
Design and Test of Nano Devices, Circuits and Systems, 2008 IEEE International Workshop on, pp. 3--6

Technology exploration for graphene nanoribbon FETs
Mihir Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
Proceedings of the 45th Annual Design Automation Conference, pp. 272--277, 2008

Tunable transient filters for soft error rate reduction in combinational circuits
Quming Zhou, Mihir R Choudhury, Kartik Mohanram
Test Symposium, 2008 13th European, pp. 179--184

Computational model of edge effects in graphene nanoribbon transistors
Pei Zhao, Mihir Choudhury, Kartik Mohanram, Jing Guo
Nano Research 1(5), 395--402, Springer, 2008

Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Mihir R Choudhury, Kartik Mohanram
Design, Automation and Test in Europe, 2008. DATE'08, pp. 903--908


2007

Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory
Mihir Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
Proceedings of the conference on Design, automation and test in Europe, pp. 1072--1077, 2007

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory
Mihir Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
Design, Automation \& Test in Europe Conference \& Exhibition, 2007. DATE'07, pp. 1--6

Accurate and scalable reliability analysis of logic circuits
Mihir R Choudhury, Kartik Mohanram
Design, Automation \& Test in Europe Conference \& Exhibition, 2007. DATE'07, pp. 1--6


2006

Design optimization for robustness to single-event upsets
Quming Zhou, Mihir R Choudhury, Kartik Mohanram
VLSI Test Symposium, 2006. Proceedings. 24th IEEE, pp. 6--pp

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
Mihir R Choudhury, Quming Zhou, Kartik Mohanram
Computer-Aided Design, 2006. ICCAD'06. IEEE/ACM International Conference on, pp. 204--209