Daniel Brand  Daniel Brand photo       

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Static Analysis of Software, the BEAM tool
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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2009

A novel analysis space for pointer analysis and its application for bug finding
M Buss, D Brand, V Sreedhar, S A Edwards
Science of Computer Programming, Elsevier, 2009


2008

Flexible pointer analysis using assign-fetch graphs
M Buss, D Brand, V Sreedhar, S A Edwards
Proceedings of the 2008 ACM symposium on Applied computing, pp. 234--239


2007

Evidence-based analysis and inferring preconditions for bug detection
D Brand, M Buss, V C Sreedhar
IEEE International Conference on Software Maintenance, 2007, pp. 44--53


2003

Arithmetic reasoning for static analysis of software
D Brand, F Krohm
Research Report RC22905, 2003


2002

Early analysis tools for system-on-a-chip design-References
JA Darringer, RA Bergamaschi, S Bhattacharya, D Brand, A Herkersdorf, JK Morrell, II Nair, P Sagmeister, Y Shin
IBM Journal of Research and Development 46(6), 2002

Early analysis tools for system-on-a-chip design
JA Darringer, RA Bergamaschi, S Bhattacharya, D Brand, A Herkersdorf, JK Morrell, II Nair, P Sagmeister, Y Shin
IBM Journal of Research and Development 46(6), 691--707, IBM, 2002


2000

LSS: A system for production logic synthesis (Reprinted from IBM Journal of Research and Development, vol 28, 1984)
JA Darringer, JV Gerbi, WH Joyner, L Trevillyan, D Brand
IBM Journal of Research and Development 44(1-2), 万方数据资源系统, 2000

A software falsifier
D Brand
11th International Symposium on Software Reliability Engineering, pp. 8--11, 2000

LSS: a system for production logic synthesis
J A Darringer, D Brand, J V Gerbi, W H Joyner, L Trevillyan
IBM Journal of Research and Development, Vol 44 44(1-2), 157--165, IBM Corp., 2000


1999

Error detection by data flow analysis restricted to executable paths
D Brand
IBM TJ Watson Research Center, Yorktown Heights, NY, USA RC21484, 1999


1998

Don't cares in synthesis: Theoretical pitfalls and practical solutions
D Brand, R A Bergamaschi, L Stok
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems17, 285--304, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 1998


1996


Inaccuracies in gatelevel power estimation,"
D Brand, C Visweswariah
Technical Report, 1996

BooleDozer: logic synthesis for ASICs
L Stok, DS Kung, D Brand, AD Drumm, AJ Sullivan, LN Reddy, N Hieter, DJ Geiger, HH Chao, PJ Osler
IBM Journal of Research and Development 40(4), 407--430, 1996


1995

Efficient use of large don't cares in high-level and logic synthesis
RA Bergamaschi, D Brand, L Stok, M Berkelaar, S Prakash
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, pp. 278

Be careful with don't cares
D Brand, R A Bergamaschi, L Stok
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, pp. 83--86


1994

Identification of redundant delay faults
D Brand, V S Iyengar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(5), 553--565, 1994

In the driver's seat of BooleDozer
D Brand, RF Damiano, L Ginneken van, AD Drumm
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994, pp. 518--521

Incremental synthesis
D Brand
IEEE/ACM International Conference on Computer-Aided Design, 1994, pp. 14--18


1993

Exhaustive simulation need not require an exponential number of tests
D Brand
IEEE Transactions on Computer Aided Design 12(11), 1635-1641, IEEE, 1993

Minimization of AND-EXOR expressions using rewrite rules
D Brand, T Sasao
IEEE Transactions on Computers, 568--576, Published by the IEEE Computer Society, 1993

Verification of large synthesized designs
D Brand
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, pp. 537


1992

Identification of single gate delay fault redundancies
D Brand, V Iyengar
Proceedings of International Symposium on Logic Synthesis and Microprocessor Architecture, 1992

Exhaustive simulation need not require an exponential number of tests
D Brand
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, pp. 98--101


1991

The taming of synthesis
D Brand
Proceedings of the International Workshop on Logic Synthesis, MCNC, 1991

On the minimization of AND-EXOR expressions
D Brand, T Sasao
Proceedings of the International Workshop on Logic Synthesis, MCNC, 1991


1990

On the minimization of AND-EXOR expressions for multiple-valued input two-valued output functions
D Brand, T Sasao
Proceedings of the 13-th Workshop on Multiple-valued Logic, 1990

On the minimization of AND-EXOR expressions
D Brand, T Sasao
Proceedings of the 23-rd Fault Tolerant Computing Conference, 1990

A non-deterministic algorithm for minimizing AND-EXOR logical expressions
D Brand, T Sasao
Proceedings of the National Convention on Computing and Communications, 1990


1989

Pla-based synthesis without plas
D Brand
Proceedings of the International Workshop on Logic Synthesis, MCNC, 1989

Synthesis of pseudo-random pattern testable designs
VS Iyengar, D Brand
Test Conference, 1989, pp. 501--508

Method of detecting constants and removing redundant connections in a logic network
C L Berman, D Brand, L H Trevillyan
US Patent 4,816,999, 1989 - Google Patents, Google Patents
US Patent 4,816,999


1988

Hill climbing with reduced search space
D Brand
ICCAD 88: 6th International conference on computer-aided design: Technical papers, pp. 294, 1988

Applications of global flow analysis in logic synthesis
L Berman, L Trevillyan, D Brand
IEEE International Symposium on Circuits and Systems, 1988, pp. 901--904

Timing analysis using functional analysis
D Brand, V S Iyengar
IEEE Transactions on Computers 37(10), 1309--1314, 1988


1986

On typing in prolog
D Brand
ACM SIGPLAN Notices 21(1), 28--30, ACM, 1986

Timing analysis using functional relationship
D Brand, V S Iyengar
Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 126-129, IEEE, 1986

Detecting sneak paths in transistor networks
D Brand
IEEE Transactions on Computers 100(35), 274--278, 1986

Construction of optimal DCVS trees
R Nair, D Brand
IBM Res. Rep. RC-11863, IBM Thomas J. Watson Research Center, 1986

Technology adaption in logic synthesis
W H Joyner Jr, L H Trevillyan, D Brand, T A Nix, S C Gundersen
Proceedings of the 23rd ACM/IEEE Design Automation Conference, pp. 94--100, 1986


1985

An experiment in silicon compilation
V Berstis, D Brand, R Nair
Proceedings of the International Symposium on Circuits and Systems, pp. 655-658, IEEE, 1985

Production logic synthesis
J Darringer, D Brand, W H Joyner Jr, L Trevillyan, J V Gerbi
Proceedings of the 1985 ACM thirteenth annual conference on Computer Science, pp. 16


1984

J. Gerbi, W. Joyner, and L. Trevillyan,“LSS: A system for production logic synthesis,”
J Daninger, D Brand
IBM J. Res. Develop28, 537--545, 1984


1983

On communicating finite-state machines
D Brand, P Zafiropulo
Journal of the ACM (JACM) 30(2), 342, ACM, 1983

Redundancy and don't cares in logic synthesis
D Brand
IEEE Transactions on Computers 100(32), 947--952, 1983


1982

PLAs Versus Random Logic
D Brand
Research Report RC-9505, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1982

Verification of HDLC
D Brand, W Joyner Jr
IEEE Transactions on Communications 30(5), 1136--1142, 1982


1980

Towards analyzing and synthesizing protocols
Pitro Zafiropulo, C West, Harry Rudin, D Cowan, Daniel Brand
Communications, IEEE Transactions on 28(4), 651-661, IEEE, 1980


1979

Completeness of conditional reductions
D Brand, J A Darringer, W H Joyner Jr
Proceedings of the, pp. 36, 1979

Symbolic simulation for correct machine design
W C Carter, W H Joyner Jr, D Brand
16th Conference on Design Automation, 1979, pp. 280--286


1978

A note on data abstractions
D Brand
ACM SIGPLAN Notices 13(1), 24, ACM, 1978

Path calculus in program verification
D Brand
Journal of the ACM (JACM) 25(4), 630--651, ACM, 1978

Verification of protocols using symbolic execution* 1
D Brand, W H Joyner, others
Computer Networks (1976) 2(4-5), 351--360, Elsevier, 1978


1977

Using Machine Descriptions in Program Verification,'
WH Joyner, WC Carter, D Brand
IBM Research Report RC692229649, 1977


1976

Analytic resolution in theorem proving
D Brand
Artificial Intelligence 7(4), 285--318, Elsevier, 1976


1975

Proving theorem with the modification method
D Brand
SIAM Journal on Computing4, 412--430, SIAM, 1975


1974

When is a matrix positive
D Brand
Canadian Mathematical Bulletin 17(3), 409-410, 1974