Daniel Friedman  Daniel Friedman photo       

contact information

Sr. Mgr., Communication Circuits and Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Member  |  IEEE Solid State Circuits Society


2013

A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing
Bodhisatwa Sadhu, MarkA Ferriss, ArunS Natarajan, Soner Yaldiz, J-O Plouchart, Alexander V Rylyakov, Alberto Valdes-Garcia, BenjaminD Parker, Aydin Babakhani, Scott Reynolds, others
IEEE, 2013

A 0.1 pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert Montoye, Leland Chang, Jose Tierno, Daniel Friedman
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, pp. 400--401

A linearized voltage-controlled oscillator for dual-path phase-locked loops
Glenn ER Cowan, Mounir Meghelli, Daniel Friedman
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, pp. 2678--2681


2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS
Ankur Agrawal, John F Bulzacchelli, Timothy O Dickson, Yong Liu, Jos\'e A Tierno, Daniel J Friedman
IEEE, 2012

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects
T. O. Dickson, Y. Liu, S. V. Rylov, B. Dang, C. K. Tsang, P. S. Andry, J. F. Bulzacchelli, H. A. Ainspan, X. Gu, L. Turlapati, M. P. Beakes, B. D. Parker, J. U. Knickerbocker, D. J. Friedman
IEEE Journal of Solid-State Circuits 47(4), 884-896, 2012

A 3.2 GS/s 4.55 b ENOB two-step subranging ADC in 45nm SOI CMOS
J-O Plouchart, Mihai AT Sanduleanu, Z Toprak-Deniz, Troy J Beukema, S Reynolds, Benjamin D Parker, M Beakes, Jos\'e A Tierno, D Friedman
Custom Integrated Circuits Conference (CICC), 2012 IEEE, pp. 1--4

A 23.5 GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
J-O Plouchart, M Ferriss, A Natarajan, A Valdes-Garcia, B Sadhu, A Rylyakov, B Parker, M Beakes, A Babakani, S Yaldiz, others
Custom Integrated Circuits Conference (CICC), 2012 IEEE, pp. 1--4

An integral path self-calibration scheme for a 20.1--26.7 GHz dual-loop PLL in 32nm SOI CMOS
Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jos\'e Tierno, others
2012 Symposium on VLSI Circuits (VLSIC), pp. 176--177

A 21.8--27.5 GHz PLL in 32nm SOI using Gm linearization to achieve- 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
Bodhisatwa Sadhu, Mark A Ferriss, Jean-Olivier Plouchart, Arun S Natarajan, Alexander V Rylyakov, Alberto Valdes-Garcia, Benjamin D Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, others
2012 IEEE Radio Frequency Integrated Circuits Symposium, pp. 75--78

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
John F Bulzacchelli, Christian Menolfi, Troy J Beukema, Daniel W Storaska, Juergen Hertle, David R Hanson, P-H Hsieh, Sergey V Rylov, Daniel Furrer, Daniele Gardellini, others
IEEE, 2012

A compact low-power 3D I/O in 45nm CMOS
Yong Liu, Wing Luk, Daniel Friedman
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 142--144


2011

Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage
Zeynep Toprak-Deniz, John Bulzacchelli, Todd Rasmus, Joseph Iadanza, William Bucossi, Seongwon Kim, Rafael Blanco, Carrie Cox, Mohak Chhabra, Christopher Leblanc, others
VLSI Circuits (VLSIC), 2011 Symposium on, pp. 274--275

High-density silicon carrier transmission line design for chip-to-chip interconnects
X. Gu, L. Turlapati, B. Dang, C. K. Tsang, P. S. Andry, T. O. Dickson, M. P. Beakes, J. U. Knickerbocker, D. J. Friedman
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, pp. 27-30


2010

A DPLL-based per core variable frequency clock generator for an eight-core POWER7 microprocessor
Jose Tierno, Alexander Rylyakov, Daniel Friedman, Ann Chen, Anthony Ciesla, Timothy Diemoz, George English, David Hui, Keith Jenkins, Paul Muench, others
VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 85--86


2009

A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
Timothy O Dickson, John F Bulzacchelli, Daniel J Friedman
Solid-State Circuits, IEEE Journal of 44(4), 1298--1305, IEEE, 2009

A 19Gb/s 38mW 1-Tap Speculative DFE receiver in 90nm CMOS
Didem Z Turker, Alexander Rylyakov, Daniel Friedman, Sudhir Gowda, Edgar Sanchez-Sinencio
VLSI Circuits, 2009 Symposium on, pp. 216--217

A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS
Byungsub Kim, Yong Liu, Timothy O Dickson, John F Bulzacchelli, Daniel J Friedman
Solid-State Circuits, IEEE Journal of 44(12), 3526--3538, IEEE, 2009

A 78mW 11.1 Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
John F Bulzacchelli, Timothy O Dickson, Zeynep Toprak Deniz, Herschel A Ainspan, Benjamin D Parker, Michael P Beakes, Sergey V Rylov, Daniel J Friedman
Solid-State Circuits Conference-Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 368--369

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
Alexander Rylyakov, J Tierno, H Ainspan, J-O Plouchart, J Bulzacchelli, Zeynep Toprak Deniz, D Friedman
Solid-State Circuits Conference-Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 94--95


2008

A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI
Jose A Tierno, Alexander V Rylyakov, Daniel J Friedman
Solid-State Circuits, IEEE Journal of 43(1), 42--51, IEEE, 2008


2007

An ultra-compact differentially tuned 6-GHz CMOS LC-VCO with dynamic common-mode feedback
Babak Soltanian, Herschel Ainspan, Woogeun Rhee, Daniel Friedman, Peter R Kinget
Solid-State Circuits, IEEE Journal of 42(8), 1635--1641, IEEE, 2007

Impact of SOI History Effect on Random Data Signals
KA Jenkins, S Kim, SP Kowalczyk, D Friedman
Integrated Circuit Design and Technology, 2007. ICICDT'07. IEEE International Conference on, pp. 1--4

All-digital dynamic self-detection and self-compensation of static phase offsets in charge-pump PLLs
Yong Liu, Woogeun Rhee, Daniel Friedman, Donhee Ham
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 176--595

A wide power-supply range (0.5 V-to-1.3 V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
AV Rylyakov, JA Tierno, GJ English, D Friedman, M Megheli
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 172--173

A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE
Azita Emami-Neyestanak, Aida Varzaghani, John F Bulzacchelli, Alexander Rylyakov, C-KK Yang, Daniel J Friedman
Solid-State Circuits, IEEE Journal of 42(4), 889--896, IEEE, 2007

A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application
Woogeun Rhee, Herschel Ainspan, Daniel J Friedman, Todd Rasmus, Stacy Garvin, Clay Cranford
Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, pp. 63--66

Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links
John F Bulzacchelli, Alexander V Rylyakov, Daniel J Friedman
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE, pp. 507--510


2006

A low-power receiver with switched-capacitor summation DFE
Azita Emami-Neyestanak, Aida Varzaghani, John Bulzacchelli, Alexander Rylyakov, CK Yang, Daniel Friedman
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, pp. 192--193

Phase and amplitude pre-emphasis techniques for low-power serial links
James F Buckwalter, Mounir Meghelli, Daniel J Friedman, Ali Hajimiri
Solid-State Circuits, IEEE Journal of 41(6), 1391--1399, IEEE, 2006

A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
M Meghelli, S Rylov, J Bulzacchelli, W Rhee, A Rylyakov, H Ainspan, B Parker, M Beakes, A Chung, T Beukema, others
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, pp. 213--222


2004

A semi-digital delay-locked loop using an analog-based finite state machine
Woogeun Rhee, Benjamin Parker, Daniel Friedman
Circuits and Systems II: Express Briefs, IEEE Transactions on 51(11), 635--639, IEEE, 2004


2003

A 0.18-$\mu$m SiGe BICMOS receiver and transmitter chipset for SONET OC-768 transmission systems
Mounir Meghelli, Alexander V Rylyakov, Steven J Zier, Michael Sorna, Daniel Friedman
Solid-State Circuits, IEEE Journal of 38(12), 2147--2154, IEEE, 2003

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]
Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander Rylyakov, Young Kwark, Daniel Friedman
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, pp. 313--316

SiGe BiCMOS integrated circuits for high-speed serial communication links
Daniel J Friedman, Mounir Meghelli, Benjamin D Parker, Jungwook Yang, Herschel A Ainspan, AV Rylyakov, Young Hoon Kwark, Mark B Ritter, Lei Shan, Steven J Zier, others
IBM Journal of Research and Development 47(2.3), 259--282, IBM, 2003


2001

A single-chip 12.5 Gbaud transceiver for serial data communication
Daniel Friedman, Mounir Meghelli, Ben Parker, Jungwook Yang, Herschel Ainspan, Mehmet Soyuer
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on, pp. 145--148

Noise performance and considerations for integrated RF/analog/mixed-signal design in a high-performance SiGe BiCMOS technology
D Greenberg, S Sweeney, C LaMothe, K Jenkins, D Friedman, B Martin Jr, G Freeman, D Ahlgren, S Subbanna, A Joseph
Electron Devices Meeting, 2001. IEDM'01. Technical Digest. International, pp. 22--1


2000

Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication
Daniel Friedman, Mounir Meghelli, Ben Parker, Herschel Ainspan, Mehmet Soyuer
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on, pp. 132--135


1997

A low-power CMOS integrated circuit for field-powered radio frequency identification tags
D Friedman, H Heinrich, D-W Duan
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International, pp. 294--295