Bruce M. Fleischer  Bruce M. Fleischer photo       

contact information

'splorin the world between power and ground
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash2016

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2015


Exposed-pipeline processing element with rollback
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent 8,990,620

Main processor support of tasks performed in memory
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent 9,104,465

Sequential location accesses in an active memory device
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent 9,104,532

Address generation in an active memory device
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent 9,110,778

Active buffered memory
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent 9,003,160


2014

Automated critical area allocation in a physical synthesized hierarchical design
Bruce M Fleischer, David J Geiger, Hung C Ngo, Ruchir Puri, Haoxing Ren
US Patent 8,656,332


2013

On-chip traffic prioritization in memory
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/761,252

Local bypass for in memory computing
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam
US Patent App. 13/837,909

Register file soft error recovery
Bruce M Fleischer, Thomas W Fox, Charles D Wait, Adam J Muff, Alfred T Watson III
US Patent 8,560,924

Chaining between exposed vector pipelines
Thomas W Fox, Bruce M Fleischer, Hans M Jacobson, Ravi Nair
US Patent App. 13/966,408

Power management for a computer system
Pradip Bose, Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/837,655


2012


Packed load/store with gather/scatter
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Jaime H Moreno, Ravi Nair, Daniel A Prener
US Patent App. 13/566,141

Memory page management
Bruce M Fleischer, Hans M Jacobson, Ravi Nair
US Patent App. 13/655,505

Predication in a vector processor
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/569,349

Vector register file
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/572,886

Active memory device gather, scatter, and filter
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent App. 13/674,520

Vector processing in an active memory device
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair, Daniel A Prener
US Patent App. 13/569,359

Low latency data exchange
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/685,816


2011



Method and system for a wiring-efficient permute unit
Bruce M Fleischer, Hung C Ngo, Jun Sawada
US Patent 8,069,195


2010

Scheme to optimize scan chain ordering in designs
Mark A Erle, Bruce M Fleischer, Daniel Lipetz
US Patent 7,721,171

System and method for performing decimal to binary conversion
Steven R Carlough, Bruce M Fleischer, Wen H Li, Eric M Schwarz
US Patent 7,660,838


System and method for a floating point unit with feedback prior to normalization and rounding
Bruce M Fleischer, Juergen Haess, Michael Kroener, Martin S Schmookler, Eric M Schwarz, Son Dao-Trong
US Patent 7,730,117


2008



2005

Processor design for extended-precision arithmetic
Robert F Enenkel, Fred G Gustavson, Bruce M Fleischer, Jose E Moreira
US Patent 6,842,765


2004

Floating point bypass register to resolve data dependencies in pipelined instruction sequences
Rainer Clemen, Guenter Gerwig, Jergen Haess, Harald Mielich, Bruce Martin Fleischer, Eric Mark Schwarz, Leon Jacob Sigal
US Patent App. 10/752,957


2000

Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
Michael Patrick Beakes, Barbara Alana Chappell, Terry Ivan Chappell, Gary S Ditlow, Barry Lee Dorfman, Bruce Martin Fleischer, Vinod Narayanan, Robert Alan Philhower, George Anthony Sai Halasz, Ghavam Ghavami Shahidi, others
US Patent 6,131,182


1999

Compiled self-resetting CMOS logic array macros
Michael Patrick Beakes, Barbara Alana Chappell, Terry Ivan Chappell, Gary S Ditlow, Barry Lee Dorfman, Bruce Martin Fleischer, Vinod Narayanan, David James Widiger
US Patent 6,005,416


1998

Methodology to test pulsed logic circuits in pseudo-static mode
Michael Patrick Beakes, Barbara Alane Chappell, Terry Ivan Chappell, Bruce Martin Fleischer, Rudolf Adriaan Haring, Talal Kamel Jaber, Edward Seewann
US Patent 5,748,012

Recurrent adrithmetical computation using carry-save arithmetic
Ramesh Chandra Agarwal, Bruce Martin Fleischer, Fred Gehrung Gustavson
US Patent 5,751,619


1997

Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability
Michael P Beakes, Barbara A Chappell, Terry I Chappell, Bruce M Fleischer, Thao N Nguyen
US Patent 5,633,820


1995

Fast comparator circuit
Barbara A Chappell, Terry I Chappell, Bruce M Fleischer, Stanley E Schuster
US Patent 5,471,188


1993



Year Unknown