Gi-Joon Nam  Gi-Joon Nam photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash3180

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Professional Associations

Professional Associations:  ACM  |  IEEE  |  Korean-American Scientiests and Engineers Association


2014

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations
Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R Nassif, Jerry Hayes
Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, pp. 382--388

Applying VLSI EDA to Energy Distribution System Design
Sani Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 91--96

Opportunities in power distribution network system optimization: from EDA perspective
Gi-Joon Nam, Sani Nassif
Proceedings of the 2014 on International symposium on physical design, pp. 149--150


2013

Wire delay variability in nanoscale technology and its impact on physical design
Sani R Nassif, Gi-Joon Nam, Shayak Banerjee
Quality Electronic Design (ISQED), 2013 14th International Symposium on, pp. 591--596


2012

An Accurate Sparse-Matrix based Framework for Statistical Static Timing Analysis
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan
Integration45(4), 3650375, 2012

Placement: hot or not?
Charles Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I Ward
Proceedings of the International Conference on Computer-Aided Design, pp. 283--290, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing
Zhuo Li, Charles J Alpert, Gi-Joon Nam, Cliff Sze, Natarajan Viswanathan, Nancy Y Zhou
Proceedings of the 49th Annual Design Automation Conference, pp. 465--470, 2012


2011

An accurate sparse-matrix based framework for statistical static timing analysis
A Ramalingam, A K Singh, S R Nassif, G J Nam, M Orshansky, D Z Pan
Integration, the VLSI Journal, Elsevier, 2011

Physical Synthesis with Clock-network Optimization for Large SoCs
D Papa, C Alpert, C Sze, Z Li, N Viswanathan, G Nam, I Markov
Micro, IEEE pp. 99, 1--1, IEEE, 2011

Floorplanning challenges in early chip planning
Jeonghee Shin, John A Darringer, Guojie Luo, Merav Aharoni, Alexey Y Lvov, G Nam, Michael B Healy
SOC Conference (SOCC), 2011 IEEE International, pp. 388--393

The ISPD-2011 routability-driven placement contest and benchmark suite
N Viswanathan, C J Alpert, C Sze, Z Li, G J Nam, J A Roy
Proceedings of the 2011 international symposium on Physical design, pp. 141--146


2010

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
S Paik, G J Nam, Y Shin
Proceedings of the International Conference on Computer-Aided Design, pp. 640--646, 2010

Detecting tangled logic structures in VLSI netlists
T Jindal, C J Alpert, J Hu, Z Li, G J Nam, C B Winn
Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 603--608

New placement prediction and mitigation techniques for local routing congestion
T Taghavi, Z Li, C Alpert, G J Nam, A Huber, S Ramji
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on, pp. 621--624

Design-hierarchy aware mixed-size placement for routability optimization
Y L Chuang, G J Nam, C J Alpert, Y W Chang, J Roy, N Viswanathan
Proceedings of the International Conference on Computer-Aided Design, pp. 663--668, 2010

Detecting tangled logic structures in VLSI netlists
T Jindal, C J Alpert, J Hu, Z Li, G J Nam, C B Winn
Proceedings of the 47th Design Automation Conference, pp. 603--608, 2010

What makes a design difficult to route
C J Alpert, Z Li, M Moffitt, G Nam, J Roy, G Tellez
Proceedings of the 19th international symposium on Physical design, pp. 7--12, 2010

ITOP: Integrating timing optimization within placement
N Viswanathan, G J Nam, J A Roy, Z Li, C J Alpert, S Ramji, C Chu
Proceedings of the 19th international symposium on Physical design, pp. 83--90, 2010


2009

SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM
G J Nam, S Ramji, T Taghavi, P G Villarrubia
US Patent App. 12/ ..., 2009 - Google Patents, Google Patents
US Patent App. 12/359,369

Clocking and the ISPD’09 clock synthesis contest
CN Sze, P Restle, GJ Nam, CJ Alpert
International Symposium on Physical Design (ISPD), pp. 149--150, 2009

CRISP: congestion reduction by iterated spreading during placement
J A Roy, N Viswanathan, G J Nam, C J Alpert, I L Markov
Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 357--362

Ispd2009 clock network synthesis contest
Cliff N Sze, Phillip Restle, Gi-Joon Nam, Charles Alpert
Proceedings of the 2009 international symposium on Physical design, pp. 149--150


2008

14 Placement: Introduction/Problem Formulation
G J Nam, P G Villarrubia
Handbook of Algorithms for Physical Design Automation, 277, Auerbach Publications, 2008

RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm
D A Papa, T Luo, M D Moffitt, CN Sze, Z Li, G J Nam, C J Alpert, I L Markov
Proceedings of the 2008 international symposium on Physical design, pp. 2156--2168, IEEE

Legalization of VLSI circuit placement with blockages using hierarchical row slicing
C J Alpert, M W Dotson, G J Nam, S Ramji, N Viswanathan
US Patent App. 12/ ..., 2008 - Google Patents, Google Patents
US Patent App. 12/108,599

The ISPD global routing benchmark suite
G J Nam, C Sze, M Yildiz
Proceedings of the 2008 international symposium on Physical design, pp. 156--159

RUMBLE: An Incremental, Timing Driven, Physical-Synthesis Optimization Algorithm
DAVID A PAPA, Tao Luo, MICHAEL D MOFFITT, Chin Ngai Sze (CLIFF), ZHUO LI, Gi
Joon Nam, Charles Alpert, Igor Markov - TCAD 2008 - IEEE Transactions on Computer-Aided Design


2007

Performance modeling for early analysis of multi-core systems
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp. 209--214, 2007

Techniques for fast physical synthesis
C J Alpert, S K Karandikar, Z Li, G J Nam, S T Quay, H Ren, CN Sze, P G Villarrubia, M C Yildiz
Proceedings of the IEEE 95(3), 573--599, IEEE, 2007

Diffusion-based placement migration with application on legalization
H. Ren, D.Z. Pan, C.J. Alpert, P.G. Villarrubia, G.J. Nam
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 26(12), 2158--2172, IEEE, 2007

ISPD 2005/2006 Placement Benchmarks
G J Nam, C Alpert, P Villarrubia
Modern Circuit Placement, 3--12, Springer, 2007

ISPD'07 global routing contest and placement contest updates
G J Nam
International Symposium on Physical Design: Proceedings of the 2007 international symposium on Physical design

The nuts and bolts of physical synthesis
C J Alpert, S Karandikar, Z Li, G J Nam, S Quay, H Ren, C Sze, P G Villarrubia, M Yildiz
Proceedings of the 2007 international workshop on System level interconnect prediction, pp. 89--94

RQL: Global placement via relaxed quadratic spreading and linearization
N Viswanathan, G J Nam, C J Alpert, P Villarrubia, H Ren, C Chu
44th ACM/IEEE Design Automation Conference, 2007, pp. 453--458

ISPD placement contest updates and ISPD 2007 global routing contest
G J Nam, M Yildiz, D Z Pan, P H Madden
Proceedings of the 2007 international symposium on Physical design, pp. 167

Hippocrates: First-do-no-harm detailed placement
H. Ren, D.Z. Pan, C.J. Alpert, G.J. Nam, P. Villarrubia
Proceedings of the 2007 Asia and South Pacific Design Automation Conference, pp. 141--146

Modern circuit placement: best practices and results
J Cong, G J Nam
2007 - books.google.com, Springer Verlag


2006

A fast hierarchical quadratic placement algorithm
G J Nam, S Reda, C J Alpert, P G Villarrubia, A B Kahng
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 25(4), 678--691, IEEE, 2006

Clock Aware Placement
C J Alpert, D J Hathaway, W R Migatz, G J Nam, H Ren, P G Villarrubia
US Patent App. 11/ ..., 2006 - Google Patents, Google Patents
US Patent App. 11/554,637

Constrained detailed placement
C J Alpert, G J Nam, H Ren, P G Villarrubia
US Patent App. 11/ ..., 2006 - Google Patents, Google Patents
US Patent App. 11/554,235

The ISPD 2006 placement contest and benchmark suite
G J Nam, CJ Aplert, P G Villarrubia
Slides presented at ISPD’06, 2006

An accurate sparse matrix based framework for statistical static timing analysis
A Ramalingam, G J Nam, A K Singh, M Orshansky, S R Nassif, D Z Pan
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 236

ISPD 2006 placement contest: Benchmark suite and results
G J Nam
Proceedings of the 2006 international symposium on Physical design, pp. 167


2005

Method and apparatus for testing routability
G J Nam, S S Kalman, J H Anderson, R Jayaraman, S K Nag, J Zhuang, others
US Patent ..., 2005 - Google Patents, Google Patents
US Patent 6,877,040

Electrical optimization for physical synthesis
G J Nam, P Groeneveld, P Parakh
Annual ACM IEEE Design Automation Conference: Proceedings of the 42 nd annual conference on Design automation, 2005

Two-Dimensional Position Detection System with MEMS Accelerometers, Readout Circuitry and Microprocessor for Padless Mouse Applications
Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim and Alan J. Drake
IEEE Transactions on VLSI System13(10), 1167-1178, 2005

2005 ISPD placement contest
G Nam
International Symposium on Physical Design: Proceedings of the 2005 international symposium on Physical design

Placement stability metrics
C J Alpert, G J Nam, P Villarribua, M C Yildiz
Design Automation Conference, 2005, pp. 1144--1147

A semi-persistent clustering technique for VLSI circuit placement
C Alpert, A Kahng, G J Nam, S Reda, P Villarrubia
Proceedings of the 2005 international symposium on Physical design, pp. 200--207

The ISPD2005 placement contest and benchmark suite
G J Nam, C J Alpert, P Villarrubia, B Winter, M Yildiz
Proceedings of the 2005 international symposium on Physical design, pp. 220


2004

Clustering-based multilevel quadratic placement
C J Alpert, G J Nam, P G Villarrubia
US Patent App. 10/896,495, 2004 - Google Patents, Google Patents
US Patent App. 10/896,495

Clustering techniques for faster and better placement of VLSI circuits
C J Alpert, G J Nam, S M Reda, P G Villarrubia
US Patent App. 10/ ..., 2004 - Google Patents, Google Patents
US Patent App. 10/996,293


2003

Latch placement technique for reduced clock signal skew
C J Alpert, G R Ellis, G J Nam, P G Villarrubia
US Patent App. 10/ ..., 2003 - Google Patents, Google Patents
US Patent App. 10/621,950

Effective free space management for cut-based placement via analytical constraint generation
C Alpert, G J Nam, P Villarrubia
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 22(10), 1343--1353, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2003


2002

Free space management for cut-based placement
C J Alpert, G J Nam, P G Villarrubia
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 746--751

A new FPGA detailed routing approach via search-based Boolean satisfiability
G J Nam, K A Sakallah, R A Rutenbar
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(6), 674--684, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2002

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
G J Nam, K Sakallah, R Rutenbar
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 581--588, Springer, 2002


2001

A boolean-based layout approach and its application to fpga routing
G J Nam
2001 - portal.acm.org, University of Michigan Ann Arbor, MI, USA

A comparative study of two Boolean formulations of FPGA detailed routing constraints
G J Nam, F Aloul, K Sakallah, R Rutenbar
Proceedings of the 2001 international symposium on Physical design, pp. 222--227




1999

Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT
G J Nam, K A Sakallah, R A Rutenbar
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, pp. 167--175


Year Unknown

ICCAD 2013 Executive Committee
J\"org Henkel, Alan J Hu, Yao-Wen Chang, Diana Marculescu, Frank Liu, Iris Bahar, Youngsoo Shin, Helmut Graeb, Patrick Madden, Gi-Joon Nam
ieeexplore.ieee.org, 0

Satisfiability-based detailed FPGA routing
G J Nam, K A Sakallah, R A Rutenbar
Ann Arbor1001, 48109--2122


Toward the Integration of Incremental Physical Synthesis Optimizations
G J Nam, D Papa, M Moffitt, C Alpert
ieeexplore.ieee.org, 0