Hillery Hunter  Hillery Hunter photo       

contact information

IBM Fellow and Director, Accelerated Cognitive Infrastructure
TJ Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash1586

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2015

Guest Editorial Computing in Emerging Technologies (Second Issue)
Mukhopadhyay, Saibal and Bhunia, Swarup and Hunter, Hillery C and Roy, Kaushik
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5(1), 1--4, IEEE, 2015
Abstract


2014

Guest Editorial Computing in Emerging Technologies (First Issue)
Mukhopadhyay, Saibal and Bhunia, Swarup and Hunter, Hillery C and Roy, Kaushik
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4(4), 377--379, IEEE, 2014
Abstract

Adapting Server Systems for New Memory Technologies
Hillery Hunter, Luis A Lastras-Montano, Bishwaranjan Bhattacharjee
Computer pp. 9, 78--84, IEEE, 2014


2013

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, Jos\'e F Mart\'\inez
Proceedings of the 40th Annual International Symposium on Computer Architecture, pp. 48--59, 2013


2011

Changing factors in memory system design: An end-to-end look at emerging challenges
H. Hunter, K. Wright
Tutorial at HPCA-17, 2011

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
J. Stuecheli, D. Kaseridis, L.K. John, D. Daly, H.C. Hunter
IEEE Micro, Top Picks v. 31, 90--98, Published by the IEEE Computer Society, 2011


2010

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C.Hunter, Lizy K John
Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 375--384, IEEE Computer Society
Abstract

The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies
J Stuecheli, D Kaseridis, D Daly, H C Hunter, L K John
Proceedings of the The ACM IEEE International Symposium on Computer Architecture (ISCA2010)


2009

Hardware--compiler co-design for adjustable data power savings
Hillery C Hunter, Erik M Nystrom, Daniel A Connors, Wen-mei W Hwu
Microprocessors and Microsystems 33(4), 244--253, Elsevier, 2009

Memory Quicksand: Unexpected Factors in Main Memory Power Management
H. Hunter
Workshop on Energy-Efficient Design, ISCA Conference, 2009

Packing in Bits: Power, Thermal, Electrical, and Packaging Constraints in Modern Memory Systems
H. Hunter
Workshop on Emerging Memory Technologies, ISCA Conference, 2009

Memory system design and DDR3/DDR4 trends
H. Hunter
Invited Tutorial at European PRACE Supercomputing Consortium, 2009

Scalability challenges for future memory
H. Hunter, V. Srinivasan, K. Wright
Tutorial at ISCA-36, 2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
P J Klim, J Barth, W R Reohr, D Dick, G Fredeman, G Koch, H M Le, A Khargonekar, P Wilcox, J Golz, others
IEEE journal of solid-state circuits 44(4), 1216--1226, Institute of Electrical and Electronics Engineers, 2009

Hardware-Compiler Co-Design for Adjustable Data Power Savings
H C Hunter, E M Nystrom, D A Connors, W H Wen-mei
Microprocessors and Microsystems 33(4), 244--253, Elsevier, 2009


2008

Watson Women's Network Leadership: A Best Practice at IBM Research for Innovative and Effective Recruitment and Retention
N Burke, T Chao, J Chen, C-H Chen-Ritzo, CA Chess, S Chiras, D Da Silva, E Duch, E Duesterwald, M Eleftheriou, others
Women in Engineering ProActive Network, 2008

A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier
John Barth, William R Reohr, Paul Parries, Gregory Fredeman, John Golz, Stanley E Schuster, Richard E Matick, Hillery Hunter, Charles C Tanner, Joseph Harig, others
Solid-State Circuits, IEEE Journal of 43(1), 86--95, IEEE, 2008

The Next Solution
H. Hunter
Panel at the Workshop on Memory Systems Performance and Correctness, ASPLOS Conference, 2008

Does multicore change the way we should design caches? A nuts-and-bolts look at future cache design
H. Hunter
Tutorial at IEEE PACT Conference, 2008

Does multicore change the way we should design caches? A nuts-and-bolts look at future cache design
H. Hunter
Tutorial at IEEE/ACM ASPLOS Conference, 2008

Changing factors in memory system design: An end-to-end look at emerging challenges
H. Hunter and K. Wright
Tutorial at MICRO-41 , 2008

A 500MHz random cycle, 1.5ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier
8. J. Barth, W. Reohr, P. Parries, G. Fredeman, J. Golz, S. Schuster, R. Matick, H. Hunter, C. Tanner, J. Harig, H. Kim, B. Khan, J. Griesemer, R. Havreluk, K. Yanagisawa, T. Kirihata, S. Iyer
IEEE Journal of Solid State Circuits 43(1), 86-95, 2008

Watson women's network leadership: A best practice at IBM Research for innovative and effective recruitment and retention
N. Burke et al.
WEPAN National Conference, 2008

A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz, J.B. Kuang, A. Mathews, T. Luong, H. Ngo, R. Freese, H. Hunter, E. Nelson, P. Parries, T. Kirihata, S. Iyer
IEEE Symposium on VLSI Circuits, 2008


2007

A 500mhz random cycle 1.5 ns-latency, soi embedded dram macro featuring a 3t micro sense amplifier
J Barth, W Reohr, P Parries, G Fredeman, J Golz, S Schuster, R Matick, H Hunter, C Tanner, J Harig, others
IEEE International Solid-State Circuits Conference, 2007, pp. 486--617


2005

Hardware compiler co-design for adjustable data power savings
H. Hunter, E. Nystrom, D. Connors, W. Hwu
Proceedings of the Workshop on Media and Streaming Processors (at ACM/IEEE MICRO), 2005


2004

Refining performance monitor design
H. Hunter and R. Nair
Proceedings of the Workshop on Complexity-Effective Design (at ACM/IEEE ISCA), 2004

Applying scalable interprocedural pointer analysis for power reduction of embedded data storage
H Hunter, E Nystrom, S Ryoo, W Hwu
Workshop on Compilers and Tools for Constrained Embedded Systems, pp. 136--146, 2004

Matching on-chip data storage to telecommunication and media application properties
H C Hunter
2004 - portal.acm.org, University of Illinois at Urbana-Champaign Champaign, IL, USA


2003

Motivating use of memory profiling in the 3G domain
H. Hunter, C-W. Li, and W. Hwu
Proceedings of the Semiconductor Research Consortium TECHCON Conference, 2003

Memory profiling: expanding the 3G developer˙ s bag of tricks
H, Hunter and W. Hwu
Workshop on Compilers and Tools for Constrained Embedded Systems (at ACM CASES), 2003

An innovative low-power high-performance programmable signal processor for digital communications
JH Moreno, V Zyuban, U Shvadron, FD Neeser, JH Derby, MS Ware, K Kailas, A Zaks, A Geva, S Ben-David, others
IBM Journal of Research and Development 47(2-3), 299--326, IBM Corp. Riverton, NJ, USA, 2003

A new look at exploiting data parallelism in embedded systems
Jaime H Moreno, HILLERY C HUNTER
International Conference on Compiler, Architecture and Synthesis of Embedded Systems (CASES), 2003


2002

Characterization of memory activity in media and telecommunications applications
H. Hunter
M.S. Thesis, 2002

Code coverage and input variability: effects on architecture and compiler research
H C Hunter, W H W Hwu
Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 87


2001



2000

Hardware support for dynamic activation of compiler-directed computation reuse
D A Connors, H C Hunter, B C Cheng, W W Hwu
Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, pp. 222--233, 2000


Year Unknown

Memory Profiling for 3G Domain DSP Development
Hillery C Hunter, Chien-Wei Li, W Hwu Wen-mei
mei - nanosioe.ee.ntu.edu.tw, 0