Hillery Hunter  Hillery Hunter photo       

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IBM Fellow and Director, Accelerated Cognitive Infrastructure
TJ Watson Research Center, Yorktown Heights, NY USA
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2017

Implementing selective cache injection
Heidelberger, Philip and Hunter, Hillery C and Kahle, James A and Nair, Ravi
US Patent 9,582,427
Abstract


2016

Error feedback and logging with memory on-chip error checking and correcting (ECC)
Coteus, Paul W and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Lastras-Montano, Luis A and Maule, Warren E and Patel, Vipinchandra
US Patent 9,454,422
Abstract

Data retrieval from stacked computer memory
Chadha, Saurabh and Hunter, Hillery C and Kim, Kyu-hyoun and Saurabh, Abhijit and Sethuraman, Saravanan and Wright, Kenneth L
US Patent 9,389,974
Abstract

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
Bose, Pradip and Buyuktosunoglu, Alper and Guo, Xiaochen and Hunter, Hillery C and Rivers, Jude A and Srinivasan, Vijayalakshmi
US Patent 9,351,899
Abstract

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
Bose, Pradip and Buyuktosunoglu, Alper and Guo, Xiaochen and Hunter, Hillery C and Rivers, Jude A and Srinivasan, Vijayalakshmi
US Patent 9,431,084
Abstract

Interface clock frequency switching using a computed insertion delay
Coteus, Paul W and Dreps, Daniel M and Hunter, Hillery C and Kim, Kyu-hyoun and Wiedemeier, Glen A
US Patent 9,442,512
Abstract

Selective memory error reporting
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent 9,471,423
Abstract

Adaptive error correction in a memory system
DeBrosse, John K and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E and Yaari, Rona
US Patent App. 15/226,160
Abstract


2015

Extended error correction coding data storage
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E and McPadden, Adam J
US Patent App. 14/835,804
Abstract

Detecting a cryogenic attack on a memory device with embedded error correction
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/621,506
Abstract

Error vector readout from a memory device
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/724,901
Abstract

Implementing memory device with sub-bank architecture
Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent 9,064,602
Abstract

Error-correcting code distribution for memory systems
Coteus, Paul W and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E and Wright, Kenneth L
US Patent 9,189,327
Abstract

Memory device error history bit
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/707,024
Abstract

Error monitoring of a memory device containing embedded error correction
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/611,351
Abstract


2014

IMPLEMENTING REINFORCEMENT LEARNING BASED FLASH CONTROL
Michele M Franceschini, Hillery C Hunter, Ashish Jagmohan, Janani Mukundan
US Patent 20,140,359,197

Memory system with dynamic refreshing
Joab D Henderson, Hillery C Hunter, Warren E Maule, Jeffrey A Stuecheli
US Patent 8,705,307


2013

Processor with memory-embedded pipeline for table-driven computation
Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent App. 14/053,978

Dram controller for variable refresh operation timing
Hillery C Hunter, Kyu-houn Kim, Janani Mukundan
US Patent App. 13/827,691

Securing the contents of a memory device
Michele M Franceschini, Hillery C Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras-Montano, Warren E Maule
US Patent App. 13/758,442

Securing the contents of a memory drive
Michele M Franceschini, Hillery C Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras-Montano, Warren E Maule
US Patent App. 13/792,720

Techniques for performing refresh operations in high-density memories
John S Dodson, Benjiman L Goodman, Hillery C Hunter, Stephen Powell, Jeffrey A Stuecheli
US Patent 8,489,807

Computer program product for managing processing resources
Hillery C Hunter, Ronald P Luijten, Phillip Stanley-Marbell
US Patent 8,473,723

Hybrid latch and fuse scheme for memory repair
Michele M Franceschini, Hillery C Hunter, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras-Montano
US Patent App. 13/732,954


2012

Memory system connector
Paul W Coteus, Shawn A Hall, Hillery C Hunter, Douglas J Joseph, Charles A Kilmer, Kyu-hyoun Kim, Warren E Maule, Todd E Takken
US Patent App. 13/657,058

Method for optimizing refresh rate for dram
Michele M Franceschini, Hillery Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras, Moinuddin K Qureshi
US Patent App. 13/569,486

Structure for implementing dynamic refresh protocols for DRAM based cache
John E Barth, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,108,609

Dram error detection, evaluation, and correction
Michele M Franceschini, Hillery C Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras-Montano, Moinuddin K Qureshi
US Patent App. 13/710,561

Managing errors in a dram by weak cell encoding
Michele M Franceschini, Hillery C Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras-Montano, Moinuddin K Qureshi
US Patent App. 13/710,551

Dram refresh
Michele M Franceschini, Hillery Hunter, Ashish Jagmohan, Charles A Kilmer, Kyu-hyoun Kim, Luis A Lastras, Moinuddin K Qureshi
US Patent App. 13/598,001

Method and Apparatus for Performing Refresh Operations in High-Density Memories
J.S. Dodson, B.L. Goodman, H.C. Hunter, S. Powell, J.A. Stuecheli
US Patent 20,120,144,105


2011

COORDINATED WRITEBACK OF DIRTY CACHELINES
D.M. Daly, B.L. Goodman, H.C. Hunter, W.J. Starke, J.A. Stuecheli
US Patent 20,110,276,762

COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT
H.C. HUNTER, R.P. LUIJTEN, P. STANLEY-MARBELL
WO Patent WO/2011/070,506

MEMORY BUS WRITE PRIORITIZATION
D.M. Daly, B.L. Goodman, H.C. Hunter, W.J. Starke, J.A. Stuecheli
US Patent 20,110,276,763

Method and system for integrating SRAM and DRAM architecture in set associative cache
Marc R Faucher, Hillery C Hunter, William R Reohr, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 7,962,695

Method and system for implementing dynamic refresh protocols for DRAM based cache
John E Barth Jr, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,024,513

ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY
K Kim, G L Chiu, P W Coteus, D M Dreps, K C Gower, H C Hunter, C A Kilmer, W E Maule
US Patent 20,110,055,671


2010

ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
P W Coteus, D M Dreps, K C Gower, H C Hunter, C A Kilmer, K Kim, K L Wright
US Patent App. 20,100/220,536


2008

Embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/019,818


Design structure for an embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/103,290

STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
J.E. Barth, E.L. Hedberg, R.M. Houle, H.C. Hunter, P.A. Sandon, others
US Patent App. 12/116,234


2007



2003