Jaime H. Moreno  Jaime H. Moreno photo       

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Senior Manager, Data Centric High Performance Computing
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  ACM  |  ACM Distinguished Speaker   |  ACM SIGARCH  |  ACM SIGMICRO  |  IEEE   |  IEEE Computer Society


2016

The Active Memory Cube
Ravi Nair, Jaime Moreno
IEEE Micro, January/February 36(1), 10-11, IEEE, 2016
Abstract


2015

Active Memory Cube: A Processing in Memory Architecture for Exascale Systems
R. Nair et al.
IBM Journal of Research and Development 59(2/3), 2015


2014

3D stacking of high-performance processors
Philip Emma, Alper Buyuktosunoglu, Michael Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime Moreno
High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pp. 500--511

Near-Data Processing: Insights from a MICRO-46 Workshop
Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime H Moreno, Richard Murphy, Ravi Nair, Steven Swanson
Micro, IEEE 34(4), 36--42, IEEE, 2014


2009


True value: assessing and optimizing the cost of computing at the data center level
J Karidis, JE Moreira, Jaime H Moreno
6th ACM Conference on Computing Frontiers, 2009


2006

Systems on a chip: The new generation of microprocessors (in Spanish)
Jaime H Moreno
Informatica (Chile), 2006

Chip-level integration: the new frontier for microprocessor architecture
Jaime H Moreno
ACM Symposium on Parallel Algorithms and Architectures, Boston, 2006


2005

The case for microarchitectural awareness of lifetime reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers, Y Li, D Brooks, Z Hu, K Skadron, V Srinivasan, M Gschwind, others
IEEE Micro 25(3), 70--80, 2005

Innovation and Technology Trends
Jaime H Moreno
10th National Conference on Electronics and Information Technologies (CANIETI), Mexico, 2005


2004

Design methodology for semi custom processor cores
Victor Zyuban, Sameh W Asaad, Thomas W Fox, Anne-Marie Haen, Daniel Littrell, Jaime H Moreno
Proceedings of the 14th ACM Great Lakes symposium on VLSI, pp. 448--452, 2004


2003

An innovative low-power high-performance programmable signal processor for digital communications
JH Moreno, V Zyuban, U Shvadron, FD Neeser, JH Derby, MS Ware, K Kailas, A Zaks, A Geva, S Ben-David, others
IBM Journal of Research and Development 47(2-3), 299--326, IBM Corp. Riverton, NJ, USA, 2003

A low-power high-performance embedded DSP core with novel SIMD features
JH Derby, Jaime H Moreno, MS Ware
Global Signal Processing Conference (GPSx), 2003

Design Methodology for Low Power High Performance Semi Custom Processor Cores
V Zyuban, S Asaad, T Fox, A Haen, D Littrell, J Moreno
Technical Report, IBM Research Report, Electrical EngineeringDec. 10, 2003

A new look at exploiting data parallelism in embedded systems
Jaime H Moreno, HILLERY C HUNTER
International Conference on Compiler, Architecture and Synthesis of Embedded Systems (CASES), 2003

Reducing instruction fetch energy with backwards branch control information and buffering
J A Rivers, S Asaad, J D Wellman, J H Moreno
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 322--325

A high-performance embedded DSP core with novel SIMD features
Jeffrey H Derby, Jaime H Moreno
IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2003


2001

Turandot users guide
Jaime H Moreno, M Moudgill
IBM Research Report RC21968, 2001


2000

Turandot: a wide-issue superscalar processor model for microarchitecture exploration
M Moudgill, J Moreno, JH Moreno, JD Wellman, P Bose, L Trevillyan, John David Wellman
VLSI Design, 58--63, 2000

Trends in compilable DSP architecture
J. Glossner, J. Moreno, M. Moudgill, J. Derby, E. Hokenek, D. Meltzer, U. Shvadron, M. Ware
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on, pp. 181--199


1999


Introduction to Digital Systems
M. Ercegovac, T. Lang, Jaime H Moreno
John Wiley & Sons, New York, 1999

Validation of Turandot, a fast processor model for microarchitecture exploration
M Moudgill, P Bose, J H Moreno
Performance, Computing and Communications Conference, 1999, pp. 451--457

Environment for PowerPC microarchitecture exploration
M Moudgill, J D Wellman, J H Moreno
Micro, IEEE 19(3), 15--25, IEEE, 1999


1998

An approach for quantifying the impact of not simulating mispredicted paths
M Moudgill, J D Wellman, J H Moreno
Performance Analysis and Its Impact in Design, Citeseer, 1998


1997

ForestaPC (Scalable-VLIW) User Instruction Set Architecture
Jaime H Moreno, Kemal Ebcioglu, Mayan Moudgill, Dave Luick
1997 - domino.watson.ibm.com, IBM TJ Watson Research Center

ForestaPC user instruction set architecture
JH Moreno, K Ebcioglu, M Moudgill, D Luick
Technical Report, IBM Research Report RC20733, Yorktown Heights, NY, 1997

Compiler/architecture interaction in a tree-based VLIW processor
Jaime H Moreno, et al.
IEEE TCCA Newsletter, 1997


ForestaPC (Scalable VLIW) User Instruction Set Architecture
Jaime H Moreno, K Ebcioglu, M Moudgill, D Luick
IBM Research Report RC20733, 1997

Scalable instruction-level parallelism through tree-instructions
Jaime H Moreno, M Moudgil
11th International Conference on Supercomputing (ICS), 1997

Trace-driven performance exploration of a PowerPC 601 OLTP workload on wide superscalar processors
J H Moreno, M Moudgill, J D Wellman, P Bose, L Trevillyan
1997 - research.ibm.com, IBM TJ Watson Research Center

Simulation/Evaluation Environment for a VLIW Processor Architecture
Jaime H Moreno, et al.
IBM Journal of Research and Development, 1997


1996



An integrated approach to architectural simulation, timing and memory hierarchy evaluation
Erik Altman, R Miranda, Jaime H Moreno, CB Hall
Workshop Performance Analysis and its Impact in Design, 1996

Architecture, compiler and simulation of a tree-based VLIW processor
Jaime H Moreno, K Ebcioglu, Erik Altman, B Hall, M. Moudgill, et al.
IBM Research Report RC20495, 1996

Compiler/architecture interaction in a tree-based VLIW processor
Jaime H Moreno, K Ebcioglu, Erik Altman, SK Chen, M. Moudgill, A. Polyak
IBM Research Report RC20694, 1996


1995

Simulation/evaluation approach for a VLIW processor
Jaime H Moreno, et al.
Workshop on Performance Analysis and its Impact on Design (PAID), 1995


1994

From Scalar to Superscalar to VLIW: An Emerging Technology in Microprocessors
Jaime H Moreno
Keynote Speaker, XIV International Conference of the Chilean Computer Society, 1994


1992

Solving finite-difference problems on a digital signal processor
J. Ruiz, Jaime H Moreno
International Congress on Numerical Methods in Engineering and Applied Sciences, 1992

Matrix computations on arrays of DSPs
Jaime H Moreno, M. Medina
International Conference on Application Specific Array Processors (ASAP), 1992

MAMACG: A tool for automatic mapping of matrix algorithms onto mesh array computational graphs
D. Le, M. Ercegovac, T. Lang, Jaime H Moreno
International Conference on Application Specific Array Processors (ASAP), 1992

Matrix Computations on Systolic-type Arrays
Jaime H Moreno, T. Lang
Kluwer Publishers, Inc., Boston, 1992


1991

Linear pseudo-systolic array for partitioned matrix algorithms
Jaime H Moreno, M. Figueroa
Journal of VLSI Signal Processing, 1991

A decoupled access/execute processor for matrix algoriths: architecture and programming
Jaime H Moreno, M. Figueroa
International Conference on Application Specific Array Processors (ASAP), 1991

Modeling and simulation of a pseudo-systolic processor for matrix algorithms
Jaime H Moreno, M. Figueroa
XII International Conference of the Chilean Computer Science Society, 1991

Matrix algorithms on digital signal processors and hierarchical memory systems
Jaime H Moreno, I. Palacios, M. Medina
XII International Conference of the Chilean Computer Science Society, 1991


1990

A graph-based approach to map matrix algorithms onto application-specific multiprocessor arrays
Jaime H Moreno, T. Lang
XI International Conference of the Chilean Computer Science Society, 1990

A graph-based approach to map matrix algorithms onto local-access processor arrays
Jaime H Moreno, T. Lang
International Conference on Application Specific Array Processors (ASAP), 1990



1989

Linear array for efficient execution of partitioned matrix algorithms
Jaime H Moreno, Tomas Lang
33rd Annual Techincal Symposium, pp. 102--117, 1989

Comments on" A systolic array for computing BA/sup-1
Jaime H Moreno, Tomas Lang
Acoustics, Speech and Signal Processing, IEEE Transactions on 37(11), 1786--1789, IEEE, 1989

A linear array for partitioned execution of matrix algorithms with high utilization
Jaime H Moreno, T. Lang
SPIE Real-Time Signal Processing XII, 1989

Comparing design methods based in index-dependencies and data-dependencies
Jaime H Moreno, T. Lang
International Conference on Systolic Arrays, 1989

Comments to " A Systolic Array for Computing BA-1"
Jaime H Moreno, T Lang
IEEE Transactions on Acoustics, Speech and Signal Processing, 1989


1988

Designing Arrays for the Faddeev Algorithm
Jaime H Moreno, Tomas Lang
1988 - wmash2003.cs.ucla.edu, UCLA, Computer Science Department

Arrays for partitioned matrix algorithms: tradeoffs between cell storage and cell bandwidth
Jaime H Moreno, T. Lang
SPIE Real-Time Signal Processing XI, 1988

Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure
Jaime H Moreno
International Conference on Parallel Processing (ICPP), 1988

On partitioning the Faddeev algorithm
Jaime H Moreno, T Lang
International Conference on Systolic Arrays, 1988


1987

Design of special-purpose arrays for matrix computations: preliminary results
Jaime H Moreno, T. Lang
SPIE Real-Time Signal Processing X, 1987


1986

A multilevel pipelined processor for the Singular Value Decomposition
Jaime H Moreno, T. Lang
SPIE Real-Time Signal Processing IX, 1986

Replication and Pipelining in Multiple-Instance Algorithms
Jaime H Moreno, T. Lang
International Conference on Parallel Processing (ICPP), 1986