Pranita Kerber  Pranita Kerber photo       

contact information

Research Staff Member, Master Inventor
IBM Research



A novel analytical capacitance model for sub-10 nm interconnects
Seshadri, Indira and Huang, Huai and Kerber, Pranita and Chen, James and Clevenger, Larry
Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International, pp. 141--143


Evolution of interfacial Fermi level in In0. 53Ga0. 47As/high-$\kappa$/TiN gate stacks
Carr, Adra and Rozen, John and Frank, Martin M and Ando, Takashi and Cartier, Eduard A and Kerber, Pranita and Narayanan, Vijay and Haight, Richard
Applied Physics Letters 107(1), 012103, AIP Publishing, 2015

Super fast physics-based methodology for accurate memory yield prediction
Joshi, Rajiv V and Kim, Keunwoo and Kanj, Rouwaida and Bhoj, Ajay N and Ziegler, Matthew M and Oldiges, Phil and Kerber, Pranita and Wong, Robert and Hook, Terence and Saroop, Sudesh and others
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(3), 534--543, IEEE, 2015


(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Lu, Darsen and Morin, Pierre and Sahu, Bhagawan and Hook, Terence B and Hashemi, Pouya and Scholze, Andreas and Kim, Bomsoo and Kerber, Pranita and Khakifirooz, Ali and Oldiges, Philip and others
ECS Transactions 64(6), 337--345, The Electrochemical Society, 2014


Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length
A. Khakifirooz, K. Cheng, A. Reznicek, T. Adam, N. Loubet, H. He, J. Kuss, J. Li, P. Kulkarni, S. Ponoth, others
Electron Device Letters, IEEE pp. 99, 1--3, IEEE, 2012

Evaluation of Various Surface Cleaning Methods on Nano-structured Carbon Films using XPS
P Kulkarni, L McCullough, T Kowalewski, L M Porter, M H Engelard, D Baer
Journal of Vacuum Science and Technology, 2012


TCAD study of back-gate biasing in UTBB
T.B. Hook, S. Furkay, P. Kulkarni, F. Monsieur
SOI Conference (SOI), 2011 IEEE International, pp. 1--2

Assessment of fully-depleted planar CMOS for low power complex circuit operation
Z. Ren, S. Mehta, J. Cai, S. Wu, Y. Zhu, T. Kanarsky, S. Kanakasabapathy, LF Edge, R. Zhang, P. Lindo, others
Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 15--5

Implant approaches and challenges for 20nm node and beyond ETSOI devices
S. Ponoth, M. Vinet, L. Grenouillet, A. Kumar, P. Kulkarni, Q. Liu, K. Cheng, B. Haran, N. Posseme, A. Khakifirooz, others
SOI Conference (SOI), 2011 IEEE International, pp. 1--2

Analysis of Parasitic Resistance in Double Gate FinFETs with Different Fin Lenghts
X Yang, K Maitra, C Yeh, P Zeitzoff, M Raymond, P Kulkarni, others
IEEE Intl. SOI Conference, 2011

Implant Approaches Challenges for 20nm and below ETSOI NFET Devices
S Ponoth, M Vinet, L Grenouillet, A Kumar, P Kulkarni
IEEE Intl. SOI Conference , 2011

Impacts of back bias on ultra thin body and BOX (UTBB) devices
Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni
Symp. VLSI Technology (VLSIT), pp. 14-15, 2011

Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology
T. Yamashita, V. Basker, T. Standaert, C.C. Yeh, J. Faltermeier, T. Yamamoto, C. Lin, A. Bryant, K. Maitra, P. Kulkarni, others
IEEE Symposium of VLSI Technology (VLSIT) 2011, ECS

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High-$ kappa $/Metal-Gate nFinFETs for High-Performance Logic Applications
K Maitra, A Khakifirooz, P Kulkarni, V S Basker, J Faltermeier, H Jagannathan, H Adhikari, C C Yeh, N R Klymko, K Saenger, others
Electron Device Letters, IEEE pp. 99, 1--3, IEEE, 2011

Impact of substrate bias on GIDL for thin-BOX ETSOI devices
P Kulkarni, Q Liu, A Khakifirooz, Y Zhang, K Cheng, F Monsieur, P Oldiges
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 103--106

Critical analysis of 14nm device options
P. Oldiges, R. Muralidhar, P. Kulkarni, CH Lin, K. Xiu, D. Guo, M. Bajaj, N. Sathaye
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 5--8

High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension
A Khakifirooz, K Cheng, J Cai, A Kimball, P Kulkarni, A Reznicek, T Adam, L Edge, H Bu, B Doris, others
Electron Device Letters, IEEE 32(3), 267--269, IEEE, 2011

Sub-25nm FinFET with Advanced Fin Formation and Short Channel Effect Engineering
T. Yamashita, VS Basker, T. Standaert, CC Yeh, T. Yamamoto, K. Maitra, CH Lina, J. Faltermeier, S. Kanakasabapathy, M. Wang, others
VLSI Symp. on Tech. Dig., paper 2A-2, 2011

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08$\mu$m2 SRAM cell
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, A Reznicek, N Loubet, H He, others
VLSI Circuits (VLSIC), 2011 Symposium on, pp. 128--129

New opportunities for SiGe and Ge channel p-FETs
SW Bedell, N Daval, A Khakifirooz, P Kulkarni, K Fogel, A Domenicucci, DK Sadana
Microelectronic Engineering 88(4), 324--330, Elsevier, 2011


Strain engineering for fully-depleted SOI devices
A Khakifirooz, P Kulkarni, others
ECS Transactions 33(6), 489-499, 2010

Challenges and solutions of extremely thin SOI (ETSOI) for CMOS scaling to 22nm node and beyond
K Cheng, A Khakifirooz, P Kulkarni, others
China Semiconductor Technology International Conference (CSTIC), 2010

Extremely-thin SOI for mainstream CMOS: challenges and opportunities
A Khakifirooz, K Cheng, A Kumar, P Kulkarni, others
International Conference on Solid State Devices and Materials (SSDM), 2010

Extraction of Effective Oxide Thickness for SOI FINFETs With High-$ kappa $/Metal Gates Using the Body Effect
S Paul, F Yeh, K Maitra, C H Lin, A Kerber, P Kulkarni, H Jagannathan, V S Basker, R J Miller, H Bu
Electron Device Letters, IEEE 31(7), 650--652, IEEE, 2010

Sub-20 nm abrupt USJ formation with long ms-flash with sub-2 nm dopant motion control
KL Lee, I Lauer, P Ronsheim, D Neumayer, S McCoy, P Kulkarni, J Chan, S Skordas, Y Zhu, J Gelpey, others
Junction Technology (IWJT), 2010 International Workshop on, pp. 1--5

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
A Khakifirooz, K Cheng, B Jagannathan, P Kulkarni, J W Sleight, D Shahrjerdi, J B Chang, S Lee, J Li, H Bu, others
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp. 152--153

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS
M. Wang, P. Kulkarni, K. Cheng, A. Khakifirooz, VS Basker, H. Jagannathan, C.C. Yeh, V. Paruchuri, B. Doris, H. Bu, others
Reliability Physics Symposium (IRPS), 2010 IEEE International, pp. 1099--1104

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
Q Liu, A Yagishita, N Loubet, A Khakifirooz, P Kulkarni, T Yamamoto, K Cheng, M Fujiwara, J Cai, D Dorman, others
VLSI Technology (VLSIT), 2010 Symposium on, pp. 61--62

Extremely thin SOI (ETSOI) technology: Past, present, and future
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, LF Edge, A Kimball, S Kanakasabapathy, S Schmitz, A Reznicek, others
SOI Conference (SOI), 2010 IEEE International, pp. 1--4

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
A Khakifirooz, K Cheng, P Kulkarni, J Cai, S Ponoth, J Kuss, BS Haran, A Kimball, LF Edge, A Reznicek, others
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on, pp. 110--111

A 0.063 $\mu$m2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
VS Basker, T Standaert, H Kawasaki, C Yeh, K Maitra, T Yamashita, J Faltermeier, H Adhikari, H Jagannathan, J Wang, others
VLSI Technology (VLSIT), 2010 Symposium on, pp. 19--20


Stress Liner Proximity Technique to Enhance Carrier Mobility in High-$\kappa$ Metal Gate MOSFETs
D. Guo, K. Schonenberg, J. Chen, D. Jaeger, P. Kulkarni, U. Kwon, Y. Liang, J. Liu, L. Song, F. Arnaud, others
MRS Proceedings, 2009

Epitaxial growth and defect generation in in-situ doped high percentage SiGe
A Reznicek, TN Adam, Z Zhu, KE Fogel, J Li, L Tai, P Kulkarni, others
Solid State Devices and Materials (SSDM), 2009

Investigation of Electrical Properties of Nanostructured Carbon Films Derived from Block Copolymers
P Kulkarni, others
Synthetic Metals 159(3), 177-181, 2009

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
K Cheng, A Khakifirooz, P Kulkarni, S Kanakasabapathy, S Schmitz, A Reznicek, T Adam, Y Zhu, J Li, J Faltermeier, others
VLSI Technology, 2009 Symposium on, pp. 212--213

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, LF Edge, A Kimball, S Kanakasabapathy, K Xiu, others
Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1--4


Electrical and Photoelectrical Characterization of Undoped and S-doped Nanocrystalline Diamond Films
P Kulkarni, others
Journal of Applied Physics 103(8), 084905-13, 2008


Electrical Contacts to Undoped and S-doped Nanocrystalline Diamond Films
P Kulkarni
Electronic Materials Confeence, 2007


Contacts to Nanostructured Carbon Films
P Kulkarni, L Porter
Electronics Materials Conference, IEEE, 2005


Thermo-physical Properties of Compatibilized Poly(vinylidene fluoride) / Poly(ethylene oxide) Blends
A Langner, P Kulkarni, others
ACS NERM, 2004


Beam Damage of Poly(vinyl chloride) [PVC] Film as Observed by X-ray Photoelectron Spectroscopy
M H Engelhard, A Krishna, P Kulkarni, others
Surface Science Spectra10, 47, 2003

Year Unknown

Annealing Technology
KL Lee, I Lauer, P Ronsheim, D Neumayer, S McCoy, P Kulkarni, J Chan, S Skordas, Y Zhu, J Gelpey, others, 0