Pranita Kerber  Pranita Kerber photo       

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Research Staff Member, Master Inventor
IBM Research
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2017

ESD device compatible with bulk bias capability
Cheng, Kangguo and Doris, Bruce B and Hook, Terence B and Khakifirooz, Ali and Kerber, Pranita and Pranatharthiharan, Balasubramanian and Shahidi, Ghavam G
US Patent 9,673,190
Abstract

Semiconductor device including epitaxially formed buried channel region
Deng, Jie and Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,590,106
Abstract

Metallized junction FinFET structures
Doris, Bruce B and Kerber, Pranita and Reznicek, Alexander and Rubin, Joshua M
US Patent 9,627,410
Abstract


2016

Strained semiconductor trampoline
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander and Schepis, Dominic J
US Patent 9,391,198
Abstract

Structure and method to improve ETSOI MOSFETS with back gate
Cheng, Kangguo and Doris, Bruce B and Kerber, Pranita and Khakifirooz, Ali and Pranatharthiharan, Balasubramanian
US Patent 9,337,259
Abstract

III-V MOSFETs with halo-doped bottom barrier layer
Kerber, Pranita and Lin, Chung-Hsun and Majumdar, Amlan and Sleight, Jeffrey W
US Patent 9,530,860
Abstract

Selective importance sampling
Joshi, Rajiv V and Kanj, Rouwaida N and Kerber, Pranita
US Patent 9,460,243
Abstract

Source and drain doping profile control employing carbon-doped semiconductor material
Kerber, Pranita and Ontalus, Viorel and Wall, Donald R and Zhu, Zhengmao
US Patent 9,231,108
Abstract

Asymmetric iii-v mosfet on silicon substrate
Cheng, Cheng-Wei and Kerber, Pranita and Leobandung, Effendi and Majumdar, Amlan and Mo, Renee T and Sun, Yanning
US Patent App. 15/377,722
Abstract

Structure and method for highly strained germanium channel fins for high mobility pFINFETs
Bedell, Stephen W and Edge, Lisa F and Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,502,420
Abstract

Structure to enhance gate induced strain effect in multigate devices
Basker, Veeraraghavan S and Kerber, Pranita and Wang, Junli and Yamashita, Tenko and Yeh, Chun-Chen
US Patent 9,293,464
Abstract

Reduced resistance short-channel InGaAs planar MOSFET
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,412,865
Abstract

FinFET device with vertical silicide on recessed source/drain epitaxy regions
Fogel, Keith E and Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,391,173
Abstract

III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture
Cheng, Cheng-Wei and Kerber, Pranita and Leobandung, Effendi and Majumdar, Amlan
US Patent 9,515,165
Abstract

Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same
Ando, Takashi and Hashemi, Pouya and Kerber, Pranita and Reznicek, Alexander
US Patent 9,484,412
Abstract

High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
Ando, Takashi and Frank, Martin M and Kerber, Pranita and Narayanan, Vijay
US Patent 9,472,553
Abstract

SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent App. 15/241,287
Abstract

FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,502,408
Abstract

Semiconductor device including gate channel having adjusted threshold voltage
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 9,230,992
Abstract

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander and Schepis, Dominic J
US Patent 9,443,873
Abstract

Reduced current leakage semiconductor device
Cheng, Cheng-Wei and Kerber, Pranita and Kim, Young-Hee and Leobandung, Effendi and Sun, Yanning
US Patent 9,397,161
Abstract


2015

Structure and method for multi-threshold voltage adjusted silicon germanium alloy devices with same silicon germanium content
Hashemi, Pouya and Kerber, Pranita and Ouyang, Christine Q and Reznicek, Alexander
US Patent App. 14/921,384
Abstract

Integrated circuit diode
Cheng, Kangguo and Kerber, Pranita and Khakifirooz, Ali and Shahidi, Ghavam G
US Patent 9,059,014
Abstract

MOSFET with recessed channel film and abrupt junctions
Cheng, Kangguo and Doris, Bruce B and Kerber, Pranita and Khakifirooz, Ali
US Patent 9,059,005
Abstract

Non-uniform gate dielectric for u-shape mosfet
Kerber, Pranita and Leobandung, Effendi and Oldiges, Philip J
US Patent App. 14/626,323
Abstract

High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type iii-v semiconductor material and silicon germanium semiconductor material
Ando, Takashi and Frank, Martin M and Kerber, Pranita and Narayanan, Vijay
US Patent App. 14/828,202
Abstract

Three dimensional FET devices having different device widths
Cheng, Kangguo and Doris, Bruce B and Khakifirooz, Ali and Kerber, Pranita
US Patent 8,946,010
Abstract

Buried-channel field-effect transistors
Cheng, Kangguo and Khakifirooz, Ali and Kerber, Pranita and Ning, Tak H
US Patent App. 14/707,775
Abstract

Method and structure to enhance gate induced strain effect in multigate device
Basker, Veeraraghavan S and Kerber, Pranita and Wang, Junli and Yamashita, Tanko and Yeh, Chun-Chen
US Patent 9,105,662
Abstract

Semiconductor device having SSOI substrate with relaxed tensile stress
Basker, Veeraraghavan S and Khakifirooz, Ali and Kerber, Pranita and Reznicek, Alexander
US Patent 8,963,248
Abstract

FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 8,993,406
Abstract


2014

Non-relaxed embedded stressors with solid source extension regions in CMOS devices
Cheng, Kangguo and Doris, Bruce B and Kerber, Pranita and Khakifirooz, Ali and La Tulipe Jr, Douglas C
US Patent 8,647,939
Abstract

Integrated circuit including DRAM and SRAM/logic
Cheng, Kangguo and Doris, Bruce B and Hook, Terence B and Khakifirooz, Ali and Kulkarni, Pranita
US Patent 8,653,596
Abstract

Multi-height fin field effect transistors
Kerber, Pranita and Radens, Carl J and Saroop, Sudesh
US Patent App. 14/243,398
Abstract

Fully-depleted son
Cheng, Kangguo and Doris, Bruce B and Kerber, Pranita and Shahidi, Ghavam G
US Patent 8,742,504
Abstract

SOI device with DTI and STI
Cheng, Kangguo and Doris, Bruce B and Khakifirooz, Ali and Kerber, Pranita
US Patent 8,652,888
Abstract

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
Cheng, Kangguo and Doris, Bruce B and Khakifirooz, Ali and Kerber, Pranita and Lavoie, Christian
US Patent 8,878,311
Abstract

Inducing channel stress in semiconductor-on-insulator devices by base substrate oxidation
Cheng, Kangguo and Doris, Bruce B and Haran, Balasubramanian S and Khakifirooz, Ali and Kerber, Pranita
US Patent 8,815,694
Abstract

Reduced resistance SiGe FinFET devices and method of forming same
Kerber, Pranita and Ouyang, Qiqing C and Reznicek, Alexander
US Patent 8,895,395
Abstract


2013

Field effect transistor with asymmetric abrupt junction implant
Kerber, Pranita and Cheng, Kangguo and Doris, Bruce B and Khakifirooz, Ali
US Patent 8,551,848
Abstract

Finfet circuits with various fin heights
Quyang, Qiqing C and Kerber, Pranita and Reznicek, Alexander
US Patent App. 13/793,662
Abstract



2012

FET Devices with Oxide Spacers
Ando, Takashi and Kerber, Pranita and Yamashita, Tenko
US Patent App. 13/653,699
Abstract


Raised Source/Drain Field Effect Transistor
B.B. Doris, K. Cheng, A. Khakifirooz, P. Kulkarni
US Patent 20,120,025,282

STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
S.W. Bedell, K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni, K.L. Saenger
US Patent 20,120,068,267

Field Effect Transistor Device with Shaped Conduction Channel
Dechao Guo, Shu-jen Han, Chung-hsun Lin
US Patent 20,120,280,279

Same-Chip Multicharacteristic Semiconductor Structures
B.B. Doris, K. Cheng, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,120,049,284

SOI Trench DRAM Structure With Backside Strap
B.B. Doris, K. Cheng, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,120,025,288

METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE
K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,120,112,207

Controlled Fin-Merging for Fin Type FET Devices
K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni
US Patent 20,120,043,610

Implant free extremely thin semiconductor devices
Kangguo Cheng, Bruce B Doris, Dechao Guo, Pranita Kulkarni, Philip J Oldiges, Ghavam G Shahidi
US Patent 8,304,301



2011

THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR
K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,110,291,189

FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR
W.E. Haensch, P. Kulkarni, T. Yamashita
US Patent 20,110,298,025

Compressively Stressed FET Device Structures
K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,110,303,915

FET WITH SELF-ALIGNED BACK GATE
K. CHENG, A. KHAKIFIROOZ, P. KULKARNI, B. DORIS
WO Patent WO/2011/161,016

DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER
K. Cheng, B.B. Doris, A. Khakifirooz, P. Kulkarni, G.G. Shahidi
US Patent 20,110,291,100

STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
G. SHAHIDI, B. DORIS, A. KHAKIFIROOZ, P. KULKARNI, K. CHENG
WO Patent WO/2011/157,571

Stressed Fin-FET Devices with Low Contact Resistance
K Cheng, B B Doris, A Khakifirooz, P Kulkarni, G G Shahidi
US Patent 20,110,284,967

Method and structure for improving uniformity of passive devices in metal gate technology
Satya N Chakravarti, Dechao Guo, Wilfried Ernst-August Haensch, Pranita Kulkarni, Fei Liu, Philip J Oldiges, Keith Kwong Hon Wong
US Patent 8,053,317

RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER
K Cheng, B Doris, A Khakifirooz, P Kulkarni, G Shahidi
US Patent 20,110,254,090


2010

THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE
K. Cheng, S. Iyer, A. Khakifirooz, P. Kulkarni
US Patent App. 12/894,218

MOSFETs WITH REDUCED CONTACT RESISTANCE
B B Doris, K Cheng, A Khakifirooz, P Kulkarni
US Patent App. 12/719,934


2009

Method of forming polymer features by directed self-assembly of block copolymers
K. Cheng, B.B. Doris, P. Kulkarni, G. Shahidi
US Patent App. 12/542,771