Krishnan Kailas  Krishnan Kailas photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  ACM  |  IEEE   |  Sigma Xi


2014

3D stacking of high-performance processors
Philip Emma, Alper Buyuktosunoglu, Michael Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime Moreno
High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pp. 500--511


2009

Formal verification of correctness and performance of random priority-based arbiters
Krishnan Kailas, Viresh Paruthi, Brian Monwai
Proc. of 9th International Conference on Formal Methods in Computer-Aided Design (FMCAD 2009), pp. 101-107, IEEE


2006

Software/Hardware Co-managed Cache Optimizations
Rajiv Ravindran, Krishnan Kailas, Zehra Sura
IBM Research Report RC23998RC 23998, IBM Research Division, 2006


2005

Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance
A Swaminathan, Y Mao, M Wu, K Kailas
7th International Workshop on Information Hiding (IH 2005), Lecture Notes in Computer Science, pp. 357-371


2003

An innovative low-power high-performance programmable signal processor for digital communications
JH Moreno, V Zyuban, U Shvadron, FD Neeser, JH Derby, MS Ware, K Kailas, A Zaks, A Geva, S Ben-David, others
IBM Journal of Research and Development 47(2-3), 299--326, IBM Corp. Riverton, NJ, USA, 2003


2002

A Register File Architecture and Compilation Scheme for Clustered ILP Processors
K Kailas, M Franklin, K Ebcioglu
8th International Euro-Par Conference (Euro-Par 2002), pp. 500-511


2001

CARS: A New Code Generation Framework for Clustered ILP Processors
Krishnan Kailas, K Ebcioglu, A Agrawala
Proc. of the 7th International Symposium on High Performance Computer Architecture (HPCA-7), p.133-143, 2001


2000

An Accurate Time-management Unit for Real-time Processors
Krishnan Kailas, Ashok Agrawala
Proc. of 8th International Conference on Advance Computing and Communications (ADCOM 2000), p.79-86


1998

An eight-issue tree-VLIW processor for dynamic binary translation
K Ebcioglu, J Fritts, S Kosonocky, M Gschwind, E Altman, K Kailas, T Bright
Proc. of International Conference on Computer Design ICCD'98, pp. 488--495, 1998


1997

Temporal accuracy and modern high performance processors: A case study using Pentium Pro
Krishnan Kailas, Bao Trinh, Ashok Agrawala
University of Maryland Institute for Advanced Computer Studies, Tech report: UMIACS-TR-97-60,, 1997


1995

A Generic Architecture for Programmable Traffic Shaper for High Speed Networks
Krishnan Kailas, Ashok Agrawala, S. V. Raghavan
University of Maryland Institute for Advanced Computer Studies, Tech report: UMIACS-TR-95-75, 1995