Katsuyuki Sakuma  Katsuyuki Sakuma photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Components, Packaging and Manufacturing Technology Society  |  IEEE, Senior Member


2017

[Invited] Advanced Packaging Technology to Address Micro-bump Solder Bonding and Warpage in Large-die 3D IC using 22nm ULK Dielectrics
Katsuyuki Sakuma, John Knickerbocker
The 2017 International Conference on Solid State Devices and Materials (SSDM), pp. 397-398

Thermo-compression bonding and mass reflow assembly processes of 3D logic die stacks
P. Gagnon, C. Bergeron, R. Langlois, S. Barbeau, S. Whitehead, C. Tyberg, R. Robertazzi, K. Sakuma, M. Wordeman, M. Scheuermann
2017 IEEE 67th Electronic Components and Technology Conference (ECTC), pp. 116-122


2016

Electrostatic Perturbations from TSV Processing during 3D Integration of Advanced CMOS Technologies
C.Kothandaraman, K.Sakuma, S.A.Cohen
2016 International Conference on Solid State Devices and Materials (SSDM), pp.465-466

Fluxless Bonding Process using Thermo-compression Micro-scrub for 61 um pitch SnAg Solder 3-D interconnections
Katsuyuki Sakuma, Buck Webb, Xiao Hu Liu, John Knickerbocker, Thomas Weiss, Shidong Li, Hongqing Zhang, Conor R. Thomas, Eric Perfecto, Tingge Xu and Hongbing Lu
2016 IEEE 66th Electronic Components and Technology Conference (ECTC)


2015


3D Integration ESD Protection Design and Analysis
Souvick Mitra, Ephrem Gebreselasie, You Li, Robert Gauthier, Joel Silberman, Christy Tyberg, Katsuyuki Sakuma, Thuy Tran-Quinn, Koushik Ramachandran, Matthew Angyal
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th , IEEE
Abstract

An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates
K. Sakuma, K. Tunga, B. Webb, K. Ramachandran, M. Interrante, H. Liu, M. Angyal, D. Berger, J. Knickerbocker, S. Iyer
2015 IEEE 65th Electronic Components and Technology Conference (ECTC), pp. 318-324


2014

Les defis de l'lntegration 3D sur les larges puces
Richard Langlois, Luc Guerin, Katsuyuki Sakuma
9/ Nanotechnologies : nouveaux paradigmes associes a l'integration 3D et a l'encapsulation, 2014

Hybrid Au-Adhesive Bonding Using Planar Adhesive Structure for 3-D LSI
Masatsugu Nimura, Jun Mizuno, Shuichi Shoji, Katsuyuki Sakuma, Hiroshi Ogino, Tomoyuki Enomoto, and Akitsu Shigetou
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 4(5), 762-768, IEEE, 2014

[Book] 3D Integration Technology with TSV and IMC Bonding
Katsuyuki Sakuma
Design of 3D Integrated Circuits and Systems, pp. 1-55, CRC Press, 2014

Bonding Technologies for Chip Level and Wafer Level 3D integration
Katsuyuki Sakuma, Spyridon Skordas, Jeffrey Zitz, Eric Perfecto, William Guthrie, Luc Guerin, Richard Langlois, Hsichang Liu, Koushik Ramachandran, Wei Lin, Kevin Winstel, Sayuri Kohara, Kuniaki Sueoka, Matthew Angyal, Troy Graves-Abe, Daniel Berger, John
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th, pp. 647-654

Assembly and Packaging of Non-bumped 3D Chip Stacks on Bumped Substrates
Bing Dang, Joana Maria, Qianwen Chen, Jae-Woong Nah, Paul Andry, Cornelia Tsang, Katsuyuki Sakuma, Christy Tyberg, Raphael Robertazzi, Michael Scheuermann, Michael Gaynes, and John Knickerbocker
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th, pp. 1372-1377


2013

Study on hybrid Au--underfill resin bonding method with lock-and-key structure for 3-D integration
Nimura, Masatsugu and Mizuno, Jun and Shigetou, Akitsu and Sakuma, Katsuyuki and Ogino, Hiroshi and Enomoto, Tomoyuki and Shoji, Shuichi
IEEE Transactions on Components, Packaging and Manufacturing Technology 3(4), 558--565, IEEE, 2013

Vacuum Ultraviolet Irradiation Treatment for Reducing Gold--Gold Bonding Temperature
Okada, Akiko and Shoji, Shuichi and Nimura, Masatsugu and Shigetou, Akitsu and Sakuma, Katsuyuki and Mizuno, Jun
Materials Transactions 54(11), 2139--2143, The Japan Institute of Metals and Materials, 2013

Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack
Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Hiroyuki Mori, Yasumitsu Orii, Fumiaki Yamada, Kohei Fujihara, Junichi Takamatsu, others
3D Systems Integration Conference (3DIC), 2013 IEEE International, pp. 1--8

Vacuum Ultraviolet Irradiation Treatment for Reducing Gold-Gold Bonding Temperature
Akiko Okada, Shuichi Shoji, Masatsugu Nimura, Akitsu Shigetou, Katsuyuki Sakuma, Jun Mizuno
Materials Transactions 54(11), 2139--2143, Japan Institute of Metals, 2013

Hybrid Au-Au bonding technology using planar adhesive structure for 3D integration
Masatsugu Nimura, Jun Mizuno, Akitsu Shigetou, Katsuyuki Sakuma, Hiroshi Ogino, Tomoyuki Enomoto, Shuichi Shoji
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd, pp. 1153--1157

Study on Hybrid Au-Underfill Resin Bonding Method With Lock-and-Key Structure for 3-D Integration
Masatsugu Nimura, Jun Mizuno, Akitsu Shigetou, Katsuyuki Sakuma, Hiroshi Ogino, Tomoyuki Enomoto, Shuichi Shoji
IEEE Transactions on Components, Packaging and Manufacturing Technology 3(4), 558--565, IEEE, 2013

Flip chip assembly method employing differential heating/cooling for large dies with coreless substrates
Katsuyuki Sakuma, Edmund Blackshear, Krishna Tunga, Chenzhou Lian, Shidong Li, Marcus Interrante, Oswald Mantilla, Jae-Woong Nah
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd, pp. 667--673


2012

Hybrid solder-adhesive bonding using simple resin planarization technique for 3D LSI
M Nimura, K Sakuma, H Ogino, T Enomoto, A Shigetou, S Shoji, J Mizuno
Low Temperature Bonding for 3D Integration (LTB-3D), 2012 3rd IEEE International Workshop on, pp. 81--81

Development of 3D Chip Integration Technology
Krzysztof Iniewski (Chapter7: Katsuyuki Sakuma)
Nano-semiconductors: Devices and Technology, CRC Press, 2012

Low temperature Au-Au bonding with VUV/O 3 treatment
Akiko Okada, Masatsugu Nimura, Naoko Unami, Akitsu Shigetou, Hirokazu Noma, Katsuyuki Sakuma, Jun Mizuno, Shuichi Shoji
3D Systems Integration Conference (3DIC), 2011 IEEE International, pp. 1--5, 2012

Chip-level TSV integration for rapid prototyping of 3D system LSIs
Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi
3D Systems Integration Conference (3DIC), 2011 IEEE International, pp. 1--4, 2012

Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration
Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami
3D Systems Integration Conference (3DIC), 2011 IEEE International, pp. 1--7, 2012

Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology
Katsuyuki Sakuma, Kurt Smith, Krishna Tunga, Eric Perfecto, Thomas Wassick, Frank Pompeo, J Nah
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, pp. 430--435

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements
Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Yasumitsu Orii, Fumiaki Yamada
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2012 28th Annual IEEE, pp. 8--13

Hybrid Au-underfill resin bonding with lock-and-key structure
Masatsugu Nimura, Akitsu Shigetou, Katsuyuki Sakuma, Hiroshi Ogino, Tomoyuki Enomoto, Jun Mizuno, Shuichi Shoji
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, pp. 258--262


2011

[Book] Development of 3D chip integration technology
Katsuyuki Sakuma
https://www.crcpress.com/product/isbn/9781439848357, pp. 173-221, CRC press, 2011

Vacuum underfill technology for advanced packaging (IMPACT 2011)
M. Hoshiyama, M. Hasegawa, T. Sato, H. Yoshii, O. Suzuki, K. Kotaka, T. Nagasaka, A. Horibe, M. C. Paquet, M. Gaynes, C. Feger, K. Sakuma, J. U. Knickerbocker, Y. Orii, K. Terada, K. Ishikawa, Y. Hirayama
2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 42-46

Vacuum underfill technology for advanced packaging
A. Horibe, M. C. Paquet, M. Gaynes, C. Feger, K. Sakuma, J. U. Knickerbocker, Y. Orii, M. Hoshiyama, M. Hasegawa, T. Sato, H. Yoshii, O. Suzuki, K. Kotaka, T. Nagasaka, K. Terada, K. Ishikawa, Y. Hirayama
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp. 1003-1008

Investigations of fluxless flip-chip bonding using vacuum ultraviolet and formic acid vapor surface treatment
N Unami, H Noma, K Sakuma, A Shigetou, S Shoji, J Mizuno
Advanced Packaging Materials (APM), 2011 International Symposium on, pp. 220--225

Development trend of three-dimensional (3D) integration technology
Katsuyuki Sakuma
IEEJ Transactions on Sensors and Micromachines131, 19--25, 2011

Solder/adhesive bonding using simple planarization technique for 3D integration
Masatsugu Nimura, Jun Mizuno, Katsuyuki Sakuma, Shuichi Shoji
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, pp. 1147--1152

Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections
K Sakuma, K Toriyama, H Noma, K Sueoka, N Unami, J Mizuno, S Shoji, Y Orii
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, pp. 7--13

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack
Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Yasumitsu Orii, Fumiaki Yamada
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2011 27th Annual IEEE, pp. 125--130

Development of vacuum underfill technology for a 3D chip stack
Katsuyuki Sakuma, Sayuri Kohara, Kuniaki Sueoka, Yasumitsu Orii, Mikio Kawakami, Kazuo Asai, Yoshikazu Hirayama, John U Knickerbocker
Journal of Micromechanics and Microengineering 21(3), 035024, IOP Publishing, 2011


2010

Effects of excimer irradiation treatment on thermocompression Au--Au Bonding
Unami, Naoko and Sakuma, Katsuyuki and Mizuno, Jun and Shoji, Shuichi
Japanese Journal of Applied Physics 49(6S), 06GN12, IOP Publishing, 2010

High density 3D integration by pre-applied Inter Chip Fill
Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada
3D Systems Integration Conference (3DIC), 2010 IEEE International, pp. 1--5

Fluxless Bonding Using Vacuum Ultraviolet and Formic Acid for 3D Interconnects
Katsuyuki Sakuma, Naoko Unami, Shuichi Shoji, Jun Mizuno
Materials Research Society Symposium Proceedings, 2010

Thermal resistance evaluation of a three-dimensional (3D) chip stack
Keiji Matsumoto, Soichiro Ibaraki, Katsuyuki Sakuma, Kuniaki Sueoka, Hidekazu Kikuchi, Yasumitsu Orii, Fumiaki Yamada
Electronics Packaging Technology Conference (EPTC), 2010 12th, pp. 614--619

Effects of excimer irradiation treatment on thermocompression Au-Au bonding
Naoko Unami, Katsuyuki Sakuma, Jun Mizuno, Shuichi Shoji
Japanese Journal of Applied Physics 49(6), 2010

Investigations of cooling solutions for three-dimensional (3D) chip stacks
Keiji Matsumoto, Soichiro Ibaraki, Masaaki Sato, Katsuyuki Sakuma, Yasumitsu Orii, Fumiaki Yamada
Semiconductor Thermal Measurement and Management Symposium, 2010. SEMI-THERM 2010. 26th Annual IEEE, pp. 25--32

Effects of vacuum ultraviolet surface treatment on the bonding interconnections for flip chip and 3-D integration
Katsuyuki Sakuma, Jun Mizuno, Noriyasu Nagai, Naoko Unami, Shuichi Shoji
Electronics Packaging Manufacturing, IEEE Transactions on 33(3), 212--220, IEEE, 2010

Thermal stress analysis of 3D die stacks with low-volume interconnections
S. Kohara, K. Sakuma, Y. Takahashi, T. Aoki, K. Sueoka, K. Matsumoto, P. S. Andry, C. K. Tsang, E. J. Sprogis, J. U. Knickerbocker, Y. Orii
2010 IEEE CPMT Symposium Japan, pp. 1-4

IMC bonding for 3D interconnection
K. Sakuma, K. Sueoka, S. Kohara, K. Matsumoto, H. Noma, T. Aoki, Y. Oyama, H. Nishiwaki, P. S. Andry, C. K. Tsang, J. U. Knickerbocker, Y. Orii
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), pp. 864-871


2009

10 $mu$m fine pitch Cu/Sn micro-bumps for 3-D super-chip stack
Ohara, Yuki and Noriki, Akihiro and Sakuma, Katsuyuki and Lee, Kang-Wook and Murugesan, Mariappan and Bea, Jichoel and Yamada, Fumiaki and Fukushima, Takafumi and Tanaka, Tetsu and Koyanagi, Mitsumasa
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, pp. 1--6

Simplified 20-$mu$m pitch vertical interconnection process for 3D chip stacking
Sakuma, Katsuyuki and Nagai, Noriyasu and Saito, Mikiko and Mizuno, Jun and Shoji, Shuichi
IEEJ Transactions on Electrical and Electronic Engineering 4(3), 339--344, Wiley Online Library, 2009

Nanoscale science and technology-Copper Multilayer Interconnection Using Ultravaiolet Nanoimprint Lithography with a Double-Deck Mold and Electroplating
Noriyasu Nagai, Hiroshi Ono, Katsuyuki Sakuma, Mikiko Saito, Jun Mizuno, Shuichi Shoji
Japanese Journal of Applied Physics 48(11), 115001, 2009

Copper multilayer interconnection using ultravaiolet nanoimprint lithography with a double-deck mold and electroplating
Noriyasu Nagai, Hiroshi Ono, Katsuyuki Sakuma, Mikiko Saito, Jun Mizuno, Shuichi Shoji
Jpn J Appl Phys 48(11), 115001--115001, Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physics, 2009

Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack
Keiji Matsumoto, Soichiro Ibaraki, Katsuyuki Sakuma, Fumiaki Yamada
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, pp. 1--5

10 $\mu$m fine pitch Cu/Sn micro-bumps for 3-D super-chip stack
Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang-Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, pp. 1--6

Vacuum Ultraviolet (VUV) surface treatment process for flip chip and 3-D interconnections
K Sakuma, N Nagai, J Mizuno, S Shoji
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, pp. 641--647

Simplified 20-$\mu$m pitch vertical interconnection process for 3D chip stacking
Katsuyuki Sakuma, Noriyasu Nagai, Mikiko Saito, Jun Mizuno, Shuichi Shoji
IEEJ Transactions on Electrical and Electronic Engineering 4(3), 339--344, Wiley Online Library, 2009


2008

3D Stacked Die and Silicon Packaging with Through-Silicon Vias, Thinned Silicon, and Silicon-Silicon Interconnection Technology
Muhannad S. Bakir, James D. Meindl (Chapter 14: J. Knickerbocker, K. Sakuma, others)
Integrated Interconnect Technologies for 3D Nanoelectronic Systems, Artech House, Inc., 2008

Die-to-Wafer 3D Integration Technology for High Yield and Throughput
K Sakuma, PS Andry, CK Tsang, Y Oyama, CS Patel, K Sueoka, EJ Sprogis, JU Knickerbocker
Materials Research Society (MRS)1112, 201--210, 2008

A New Fine-Pitch Vertical Interconnection Process For Through Silicon Vias and Microbumps
K Sakuma, H Ono, N Nagai, M Saito, J Mizuno, S Shoji
Asia-Pacific Conference on Transducers and Micro-Nano Technology (APCOT), 2008

Characterization of stacked die using die-to-wafer integration for high yield and throughput
K. Sakuma, P. S. Andry, C. K. Tsang, K. Sueoka, Y. Oyama, C. Patel, B. Dang, S. L. Wright, B. C. Webb, E. Sprogis, R. Polastre, R. Horton, J. U. Knickerbocker
2008 58th Electronic Components and Technology Conference, pp. 18-23

3D chip stacking with C4 technology
B. Dang, S. L. Wright, P. S. Andry, E. J. Sprogis, C. K. Tsang, M. J. Interrante, B. C. Webb, R. J. Polastre, R. R. Horton, C. S. Patel, A. Sharma, J. Zheng, K. Sakuma, J. U. Knickerbocker
IBM Journal of Research and Development 52(6), 599-609, 2008

3D silicon integration
J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, C. S. Patel, R. J. Polastre, K. Sakuma, E. S. Sprogis, C. K. Tsang, B. C. Webb, S. L. Wright
2008 58th Electronic Components and Technology Conference, pp. 538-543

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
Katsuyuki Sakuma, Paul S Andry, Cornelia K Tsang, Steven L Wright, Bing Dang, Chirag S Patel, Bucknell C Webb, J Maria, Edmund J Sprogis, SK Kang, others
IBM Journal of Research and Development 52(6), 611--622, IBM, 2008

Three-dimensional silicon integration
J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, S. L. Wright
IBM Journal of Research and Development 52(6), 553-569, 2008


2007

Assembly, Characterization, and Reworkability of Pb-free Ultra-Fine Pitch C4s for System-on-Package
B. Dang, S. L. Wright, P. S. Andry, C. K. Tsang, C. Patel, R. Polastre, R. Horton, K. Sakuma, B. C. Webb, E. Sprogis, G. Zhang, A. Sharma, J. U. Knickerbocker
2007 Proceedings 57th Electronic Components and Technology Conference, pp. 42-48

3D chip stacking technology with low-volume lead-free interconnections
K Sakuma, PS Andry, B Dang, J Maria, CK Tsang, C Patel, SL Wright, B Webb, E Sprogis, SK Kang, others
2007 Proceedings 57th Electronic Components and Technology Conference, pp. 627--632


2000

Intelligent Image Sensor Chip with Three Dimensional Structure.
Kang-Wook Lee, T NAKAMURA, K SAKUMA, M NOBUAKI, S HIROAKI, KT PARK, H KURINO, M KOYANAGI
Report of the Institute of Image Information and Television Engineers, 35--40, 2000

Development of three-dimensional integration technology for highly parallel image-processing chip
Kang Wook Lee, Tomonori Nakamura, Katsuyuki Sakuma, Ki Tae Park, Hiroaki Shimazutsu, Nobuaki Miyakawa, Ki Yoon Kim, Hiroyuki Kurino, Mitsumasa Koyanagi
Japanese Journal of Applied Physics39, 2473, 2000


1999

A new wafer scale chip-on-chip (w-coc) packaging technology using adhesive injection method
Hiroyuki Kurino, Kang Lee, Katsuyuki Sakuma, Tomonori Nakamura, Mitsumasa Koyanagi
Japanese journal of applied physics38, 2406, 1999

Intelligent image sensor chip with three dimensional structure
H Kurino, KW Lee, T Nakamura, K Sakuma, KT Park, N Miyakawa, H Shimazutsu, KY Kim, K Inamura, M Koyanagi
Electron Devices Meeting, 1999. IEDM'99. Technical Digest. International, pp. 879--882


1998

A New Wafer-Scale Chip-on-Chip (W-COC) Packaging Technology Using Adhesive Injection Method
K. Sakuma, K.W. Lee, T. Nakamura, H. Kurino and M. Koyanagi
Extended Abstracts of the 1998 Conference on Solid State Devices and Materials (SSDM), pp. 286-297

New three dimensional integration technology for future system-on silicon LSIs
M Koyanagi, H Kurino, T Matsumoto, K Sakuma, KW Lee, N Miyakawa, H Itani, H Tsukamoto
IEEE International Workshop on Chip-Package Codesign, pp. 460--461, 1998

New three-dimensional wafer bonding technology using the adhesive injection method
Takuji Matsumoto, Masakazu Satoh, Katsuyuki Sakuma, Hiroyuki Kurino, Nobuaki Miyakawa, Hikotaro Itani, Mitsumasa Koyanagi
Japanese journal of applied physics 37(part 1), 1217--1221, 1998

Future system-on-silicon LSI chips
Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani
Micro, IEEE 18(4), 17--22, IEEE, 1998