Michael B. Healy  Michael B. Healy photo       

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Research Staff Member - Memory subsystems and 3D integration
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash1545

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Professional Associations

Professional Associations:  ACM  |  IEEE  |  IEEE Computer Society  |  IEEE HKN


2016

Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 9,336,144
Abstract

Selective memory error reporting
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent 9,471,423
Abstract

3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan Kunjunny
US Patent 9,298,672
Abstract

Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 9,336,144
Abstract

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 9,383,411
Abstract

Three-dimensional processing system having independent calibration and statistical collection layer
Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K and Buyuktosunoglu, Alper
US Patent 9,389,876
Abstract


2015

Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 9,195,630
Abstract

Memory architectures having wiring structures that enable different access patterns in multiple dimensions
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 9,190,118
Abstract

Detecting a cryogenic attack on a memory device with embedded error correction
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/621,506
Abstract

Error vector readout from a memory device
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/724,901
Abstract

Error vector readout from a memory device
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/705,115
Abstract

Error monitoring of a memory device containing embedded error correction
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/611,351
Abstract

Memory device error history bit
Healy, Michael B and Hunter, Hillery C and Kilmer, Charles A and Kim, Kyu-hyoun and Maule, Warren E
US Patent App. 14/707,024
Abstract


2014

3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
Buyuktosunoglu, Alper and Emma, Philip G and Hartstein, Allan M and Healy, Michael B and Kailas, Krishnan K
US Patent 8,799,710
Abstract