Mark Ferriss  Mark Ferriss photo       

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Research Staff Member - Communication Circuts and Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +914dash945dash2655

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2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
Ferriss, Mark and Sadhu, Bodhisatwa and Rylyakov, Alexander and Ainspan, Herschel and Friedman, Daniel
2016 IEEE International Solid-State Circuits Conference (ISSCC), pp. 196--198
Abstract


2015

A 1.4 pJ/bit, Power-Scalable 16 #x00D7;12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
T.O. Dickson, Yong Liu, S.V. Rylov, A. Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, J.F. Bulzacchelli, M. Ferriss, H.A. Ainspan, A. Rylyakov, B.D. Parker, M.P. Beakes, C. Baks, Lei Shan, Young Kwark, J.A. Tierno, D.J. Friedman
Solid-State Circuits, IEEE Journal of 50(8), 1917-1931, 2015

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance
Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia
IEEE Journal of Solid-State Circuits 50(5), 1214--1223, IEEE, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a $\Delta$$\Sigma$ noise-cancellation scheme
Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov, Herschel Ainspan, Daniel Friedman
Solid-State Circuits Conference-(ISSCC), 2015 IEEE International, pp. 1--3


2014

A 1.4-pJ/b, power-scalable 16$\times$ 12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
Timothy O Dickson, Yong Liu, Sergey V Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F Bulzacchelli, Mark Ferriss, Herschel Ainspan, Alexander Rylyakov, others
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the, pp. 1--4

A 1.4-pJ/b, power-scalable 1612-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
Dickson, T.O. ; Yong Liu ; Rylov, S.V. ; Agrawal, A. ; Seongwon Kim ; Ping-Hsuan Hsieh ; Bulzacchelli, J.F. ; Ferriss, M. ; Ainspan, H. ; Rylyakov, A. ; Parker, B.D. ; Baks, C. ; Lei Shan ; Young Kwark ; Tierno, J. ; Friedman, D.J.
CICC, 2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS
Ferriss, M. ; Rylyakov, A. ; Tierno, J.A. ; Ainspan, H. ; Friedman, D.J.
Solid-State Circuits, IEEE Journal of , IEEE, 2014

Indirect performance sensing for on-chip self-healing of analog and RF circuits
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence Pileggi, Arun Natarajan, Mark Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Ben Parker, others
IEEE Transactions on Circuits and Systems I: Regular Papers 61(8), 2243--2252, IEEE, 2014

A 46.4--58.1 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia
2014 IEEE Radio Frequency Integrated Circuits Symposium, pp. 173--176


2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, L Pileggi, A Natarajan, M Ferriss, J Plouchart, Bodhisatwa Sadhu, B Parker, others
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pp. 1--4

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS
J.-O. Plouchart, M. Ferriss, A.S. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B.D. Parker, M. Beakes, A. Babakhani, S. Yaldiz, others
IEEE Transactions on Circuits and Systems I 60(8), 2009--2017, IEEE, 2013

A 73.9--83.5 GHz synthesizer with- 111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology
J-O Plouchart, Mark Ferriss, Bodhisatwa Sadhu, Mihai Sanduleanu, Benjamin Parker, Scott Reynolds
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS
Alberto Valdes-Garcia, Arun Natarajan, Duixian Liu, Mihai Sanduleanu, Xiaoxiong Gu, Mark Ferriss, Ben Parker, Christian Baks, Jean-Olivier Plouchart, Herschel Ainspan, others
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 375--378

A 73.9-83.5GHz Synthesizer with -111dBc/Hz Phase Noise at 10MHz Offset in a 130nm SiGe BiCMOS Technology
J.-O. Plouchart, M. Ferriss, B. Sadhu, M. Sanduleanu, B. Parker, S. Reynolds
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013

A 28GHz Hybrid PLL in 32nm SOI CMOS
Mark Ferriss, Alexander Rylyakov, Herschel Ainspan, Jose Tierno, Daniel Friedman
VLSI symposia on technology and circuits, 2013

An integral path self-calibration scheme for a dual-loop PLL
Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Ben Parker, Jos\'e A Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, others
IEEE Journal of Solid-State Circuits 48(4), 996--1008, IEEE, 2013

A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing
Bodhisatwa Sadhu, MarkA Ferriss, ArunS Natarajan, Soner Yaldiz, J-O Plouchart, Alexander V Rylyakov, Alberto Valdes-Garcia, BenjaminD Parker, Aydin Babakhani, Scott Reynolds, others
IEEE, 2013


2012

A 23.5 GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
J-O Plouchart, M Ferriss, A Natarajan, A Valdes-Garcia, B Sadhu, A Rylyakov, B Parker, M Beakes, A Babakani, S Yaldiz, others
Custom Integrated Circuits Conference (CICC), 2012 IEEE, pp. 1--4

An integral path self-calibration scheme for a 20.1--26.7 GHz dual-loop PLL in 32nm SOI CMOS
Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jos\'e Tierno, others
2012 Symposium on VLSI Circuits (VLSIC), pp. 176--177

A 21.8--27.5 GHz PLL in 32nm SOI using Gm linearization to achieve- 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
Bodhisatwa Sadhu, Mark A Ferriss, Jean-Olivier Plouchart, Arun S Natarajan, Alexander V Rylyakov, Alberto Valdes-Garcia, Benjamin D Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, others
2012 IEEE Radio Frequency Integrated Circuits Symposium, pp. 75--78

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman
IEEE CICC, 2012


2011

Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators
S. Yaldiz, V. Calayir, X. Li, L. Pileggi, A. S. Natarajan, M. A. Ferriss, J. Tierno
Custom Integrated Circuits Conference, 2011

A 2.4 GHz 2Mb/s digital PLL-based transmitter for 802.15. 4 in 130nm CMOS
Mohammad Mahdi Ghahramani, Mark A Ferriss, Michael P Flynn
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, pp. 1--4


2009

A Fractional-N PLL modulator with flexible direct digital phase modulation
M. Ferriss, D. T. Lin, M. P. Flynn
Custom Integrated Circuits Conference, 2009


2008

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme
M. Ferriss, M.P. Flynn
IEEE Journal of Solid-State Circuits 43(11), 2464-2471, 2008


2007


A 14mW fractional-N PLL modulator with an enhanced digital phase detector and frequency switching scheme
M. Ferriss, M. P. Flynn
IEEE International Solid-State Circuits Conference, 2007


2005

A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback
D. DALTON, K. CHAI, E. EVANS, M. FERRISS, D. HITCHCOX, P. MURRAY, S. SELVANAYAGAM, P. SHEPHERD, L. DEVITO
IEEE journal of solid-state circuits 40(12), 2713-2725, 2005