Michael Gschwind  Michael Gschwind photo       

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Chief Engineer, Machine Learning and Deep Learning
IBM TJ Watson Research Center
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Professional Associations

Professional Associations:  ACM  |  ACM Distinguished Speaker   |  ACM SIGMICRO  |  Executive Board, ACM SIGMICRO  |  Fellow, IEEE  |  IEEE   |  IEEE Computer Society


2016

Workload acceleration with the IBM POWER vector-scalar architecture
Michael Gschwind
IBM Journal of Research and Development 60(2-3), 14:1 - 14:18, IBM, 2016
Abstract


2015

The SIMD accelerator for business analytics on the IBM z13
Schwarz, E.M. Krishnamurthy, R.B. ; Parris, C.J. ; Bradbury, J.D. ; Nnebe, I.M. ; Gschwind, M.
IBM Journal of Research and Development 59(4/5), 2015
Abstract

I/O Virtualization and System Acceleration in POWER8
Michael Gschwind
Hot Chips 2015, IEEE

IBM POWER8 processor core microarchitecture
Sinharoy, B. ; Van Norstrand, J.A. ; Eickemeyer, R.J. ; Le, H.Q. ; Leenstra, J. ; Nguyen, D.Q. ; Konigsburg, B. ; Ward, K. ; Brown, M.D. ; Moreira, J.E. ; Levitan, D. ; Tung, S. ; Hrusecky, D. ; Bishop, J.W. ; Gschwind, M. ; Boersma, M. ; Kroener, M. ; K
IBM Journal of Research and Development 59(1), IBM, 2015


2014




2012

Blue Gene/Q: by co-design
Blue Gene Team
Computer Science - Research and Development, Springer Verlag, 2012

Blue Gene/Q: design for sustained multi-petaflop computing
M. Gschwind
Proceedings of the 26th ACM international conference on Supercomputing, pp. 245--246, 2012

The IBM Blue Gene/Q Compute Chip
R.A. Haring, M. Ohmacht, T.W. Fox, M.K. Gschwind, D.L. Satterfield, K. Sugavanam, P.W. Coteus, P. Heidelberger, M.A. Blumrich, R.W. Wisniewski, A. Gara, G.L.-T. Chiu, P.A. Boyle, N.H. Chist, Changhoan Kim
Micro, IEEE 32(2), 48 -60, IEEE, 2012

Guest Editorial: Parallel Systems and Compilers
Valentina Salapura, Michael Gschwind, Jens Knoop
International Journal of Parallel Programming 40(1), 1--3, Springer Netherlands, 2012


2011

SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time
Michael Gschwind, Valentina Salapura, Catherine Trammell, Sally A McKee
IEEE 29th International Conference on Computer Design (ICCD), pp. 404--410, IEEE, 2011


2010

Application Acceleration with the Cell Broadband Engine
G Shi, V Kindratenko, F Pratas, P Trancoso, M Gschwind
Computing in Science & Engineering 12(1), 76--81, IEEE, 2010


2009

High Performance Computing with the Cell Broadband Engine
Michael Gschwind, Fred Gustavson, and Jan F. Prins
Scientific Programming, 2009

Topical Issue on Hybrid Systems
M Gschwind, M Perrone
IBM Journal of Research and Development 53(5), IBM, 2009

64-bit prefix adders: Power-efficient topologies and design solutions
C Zhou, B M Fleischer, M Gschwind, R Puri
Custom Integrated Circuits Conference, pp. 179--182, 2009

Integrated execution: a programming model for accelerators
M Gschwind
IBM Journal of Research and Development 53(5), 4--1, IBM, 2009


2008

Special issue of the Journal of Parallel and Distributed Computing: General-Purpose Paralle l Processing Using GPUs
Miriam Leeser, France Daniel Connors, Michael Gschwind, David Kaeli, Nagarajan Kandasamy, Mateo Valero, Barcelona Supercomputer Center, Amitahb Varshney
J. Parallel Distrib. Comput68, 116, 2008

Cell GC: using the cell synergistic processor as a garbage collection coprocessor
C Y Cher, M Gschwind
Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments (VEE), pp. 141--150, 2008

Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
M Gschwind
ICCD - International Conference on Computer Design, pp. 478--485, 2008

Next-generation performance counters: Towards monitoring over thousand concurrent events
Valentina Salapura, Karthik Ganesan, Alan Gara, Michael Gschwind, James C Sexton, Robert E Walkup
ISPASS 2008, IEEE International Symposium on Performance Analysis of Systems and Software, pp. 139--146


2007

The cell broadband engine: exploiting multiple levels of parallelism in a chip multiprocessor
M Gschwind
International Journal of Parallel Programming 35(3), 233--262, Springer, 2007

An open source environment for cell broadband engine system software
M Gschwind, D Erb, S Manning, M Nutter
Computer 40(6), 37--47, IEEE, 2007


2006

Cell broadband engine -- enabling density computing for data-rich environments
M Gschwind, BD D'Amora, JK O'Brien, K O'Brien, AE Eichenberger, P Wu
Tutorial presented at the Annual International Symposium on Computer Architecture, 2006

Chip multiprocessing and the cell broadband engine
M Gschwind
Proceedings of the 3rd conference on Computing frontiers, pp. 1--8, 2006

Synergistic processing in cell's multicore architecture
M Gschwind, H P Hofstee, B Flachs, M Hopkin, Y Watanabe, T Yamazaki
Micro, IEEE 26(2), 10--24, IEEE, 2006

Using advanced compiler technology to exploit the performance of the Cell Broadband Engine
A. Eichenberger, J. K. O'brien, K. M. O'brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, Z. Sura, A. Wang, T. Zhang, P. Zhao, M. K. Gschwind, R. Archambault, Y. Gao, R. Koo
IBM Systems Journal 45(1), 59--84, IBM, 2006


2005

A novel SIMD architecture for the Cell heterogeneous chip-multiprocessor
M Gschwind, P Hofstee, B Flachs, M Hopkins, Y Watanabe, T Yamazaki
Hot Chips, 2005

Optimizing Compiler for the CELL Processor
J. K. O'Brien, K. M. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao, M. K. Gschwind
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 161--172, IEEE Computer Society, 2005

Power and performance optimization at the system level
Valentina Salapura, Randy Bickford, Matthias Blumrich, Arthur A Bright, Dong Chen, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta, others
Proceedings of the 2nd conference on Computing frontiers, pp. 125--132, ACM, 2005


2004

Integrated analysis of power and performance for pipelined microprocessors
P. Bose, D. Brooks, P. Emma, M. Gschwind, V. Srinivasan, P. Strenski, V. Zyuban
IEEE Transactions on Computers 53(8), 1004--1016, IEEE, 2004

BOA: A second generation DAISY architecture
E Altman, M Gschwind
Tutorial presented at 31st international symposium on computer architecture, 2004

Exploring real time multimedia content creation in video games
B Matthews, J D Wellman, M Gschwind
6th Workshop on Media and Streaming Processors, 2004


2003

Microarchitecture-level power-performance analysis: the powertimer approach
David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, P Emma, M Rosenfield
IBM J. Research and Development 47(5/6), 653--670, 2003

Early-stage definition of LPX: A low power issue-execute processor
P Bose, D Brooks, A Buyuktosunoglu, P Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, P Kudva
Power-Aware Computer Systems, pp. 89--92, Springer, 2003

New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
David Brooks, Pradip Bose, Viji Srinivasan, MK Gschwind, Philip G Emma, Michael G Rosenfield
IBM Journal of Research and Development 47(5.6), 653--670, IBM, 2003


2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor Prototype
P Bose, DM Brooks, A Buyuktosunoglu, PW Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, SE Schuster, others
Power Aware Computer Systems Workshop in conjunction with HPCA-8, 2002

Optimizing pipelines for power and performance
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, Philip G Emma
Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on, pp. 333--344


Precise exception semantics in dynamic compilation
M Gschwind, E Altman
Compiler Construction, pp. 235--252, 2002


2001

Dynamic Binary Translation and Optimization
Kemal Ebcioglu, Erik Altman, Michael Gschwind, Sumedh Sathaye
Transaction on Computers 50(6), 529--548, IEEE, 2001

FPGA prototyping of a RISC processor core for embedded applications
Michael Gschwind, Valentina Salapura, Dietmar Maurer
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 9(2), 241--250, IEEE, 2001


High frequency pipeline architecture using the recirculation buffer
M Gschwind, S Kosonocky, E Altman
IBM Research Report (RC23113), IBM, 2001

Advances and Future Challenges in Binary Translation and Optimization
Erik Altman, Kemal Ebcio u g, Michael Gschwind, Sumedh Sathaye
Proceedings of the IEEE 89(11), 1710--1722, IEEE, 2001

Optimization and Precise Exceptions in Dynamic Compilation
Michael Gschwind, Erik Altman
Computer Architecture News 29(1), 66--74, ACM, 2001


2000

Optimization and Precise Exceptions in Dynamic Compilation
Michael Gschwind, Eric R Altman
Second Workshop on Binary Translation, held in conjunction with PACT 2000


BOA: The architecture of a binary translation processor
E Altman, M Gschwind, S Sathaye, S Kosonocky, A Bright, J Fritts, P Ledak, others
Research Report RC21665, IBM TJ Watson Research Center, Yorktown Heights, NY, Citeseer, 2000

Binary translation and architecture convergence issues for IBM System/390
M Gschwind, K Ebcioglu, E Altman, S Sathaye
Proceedings of the 14th international conference on Supercomputing, pp. 336--347, 2000

Dynamic and transparent binary translation
M Gschwind, E R Altman, S Sathaye, P Ledak, D Appenzeller
Computer 33(3), 54--59, IEEE, 2000


1999

BOA: Targeting multi-gigahertz with binary translation
S. Sathaye, P. Ledak, J. LeBlanc, S. Kosonocky, M. Gschwind, J. Fritts, Z. Filan, A. Bright, D. Appenzeller, E. Altman, C. Agricola
Proc, pp. 2--11, 1999

Execution-based scheduling for VLIW architectures
K Ebcioglu, ER Altman, S Sathaye, M Gschwind
Euro-Par Conference, 1999

DAISY/390: Full System Binary Translation of IBM System/390
M Gschwind, K Ebcioglu, E Altman, S Sathaye
1999 - Citeseer, Citeseer

Efficient instruction scheduling with precise exceptions
E Altman, K Ebcioglu, M Gschwind, S Sathaye
IBM Research Report RC2295796, 100--108, Citeseer, 1999


Optimizations and oracle parallelism with dynamic translation
K Ebcioglu, E R Altman, S Sathaye, M Gschwind
Microarchitecture, 1999, pp. 284--295

Execution-based scheduling for VLIW architectures
K Ebcioglu, E Altman, S Sathaye, M Gschwind
Euro-Par 99 Parallel Processing, 1269--1280, Springer, 1999

Instruction set selection for ASIP design
M Gschwind
Hardware/Software Codesign, 1999, pp. 7--11


1998

Method and apparatus for determining branch addresses in programs generated by binary translation
Michael Gschwind
IBM Disclosures YOR819980334, Citeseer

JavaVM implementation: Compilers versus hardware
A Krall, A Ertl, M Gschwind
ACACS, pp. 101--110, 1998


Hardware/software co-design of a fuzzy RISC processor
Valentina Salapura, Michael Gschwind
Proceedings of the Conference on Design, Automation and Test in Europe, pp. 875--882, 1998

An eight-issue tree-VLIW processor for dynamic binary translation
K Ebcioglu, J Fritts, S Kosonocky, M Gschwind, E Altman, K Kailas, T Bright
Proc. of International Conference on Computer Design ICCD'98, pp. 488--495, 1998


1996

A Generic Building Block For Hopfield Neural Networks With On-chip Learning
Gschwind, M.; Salapura, V.; Maischberger, O.
1996 IEEE International Symposium on Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., , IEEE

Migration from schematic-based designs to a VHDL synthesis environment
M. Gschwind, C. Mautner
Field-Programmable Logic Smart Applications, New Paradigms and Compilers, 346--355, Springer, 1996



1995

Optimizing VHDL code for FPGA targets
Michael Gschwind, Valentina Salapura
Technical Report, Technical Report IB 95/11, Institut f. Technische Informatik, Technische Universitaet Wien, Vienna, Austria, 1995

A VHDL design methodology for FPGAs
Michael Gschwind, Valentina Salapura
Field-Programmable Logic and Applications, pp. 208--217, Springer Berlin Heidelberg, 1995

Vector prefetching
M K Gschwind, T J Pietsch
ACM SIGARCH Computer Architecture News 23(5), 1--7, ACM, 1995


1994

RAN2SOM: a reconfigurable neural network architecture based on bit stream arithmetic
Michael Gschwind, Valentina Salapura, Oliver Maischberger
Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, pp. 294 - 300, IEEE, 1994

FTP access as a user-defined file system
M K Gschwind
ACM SIGOPS Operating Systems Review 28(2), 73--80, ACM, 1994