Phil Oldiges  Phil Oldiges photo       

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Device Design & Modeling Czar
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations:  IEEE Electron Devices Society (EDS)  |  IEEE Nuclear and Plasma Sciences Society  |  IEEE, Senior Member  |  New York Academy of Science  |  Sigma Pi Sigma  |  Tau Beta Pi

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2017

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Loubet, N and Hook, T and Montanini, P and Yeung, C-W and Kanakasabapathy, S and Guillom, M and Yamashita, T and Zhang, J and Miao, X and Wang, J and others
VLSI Technology, 2017 Symposium on, pp. T230--T231
Abstract

First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance
Dixit, Hemant and Niu, Chengyu and Raymond, Mark and Kamineni, Vimal and Pandey, Rajan K and Konar, Anirudhha and Fronheiser, Jody and Carr, Adra V and Oldiges, Phil and Adusumilli, Praneet and others
IEEE Transactions on Electron Devices 64(9), 3775--3780, IEEE, 2017
Abstract

Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd
Rodbell, Kenneth P and Gordon, Michael S and Stawiasz, Kevin G and Oldiges, Phil and Lilja, Klas and Turowski, Marek
IEEE Transactions on Nuclear Science 64(3), 999--1005, IEEE, 2017
Abstract


2016

Vertical channel devices enabled by through silicon via (TSV) technologies
Kothandaraman, C and Rosenblatt, S and Safran, J and Oldiges, P and Kulkarni-Kerber, P and Xumalo, J and Landers, W and Liu, J and Oakley, JA and Butt, S and others
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 9--6
Abstract

Technology viable DC performance elements for Si/SiGe channel CMOS FinFET
Gen Tsutsui, Ruqiang Bao, Kwan-yong Lim, Robert R Robison, Reinaldo A Vega, Jie Yang, Zuoguang Liu, et al
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 17.4. 1-17.4. 4, IEEE

FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond
D. Guo, G. Karve, G. Tsutsui, K. Y. Lim, R. Robison, T. Hook, R. Vega, D. Liu, S. Bedell, S. Mochizuki, F. Lie, K. Akarvardar, M. Wang, R. Bao, S. Burns, V. Chan, K. Cheng, J. Demarest, J. Fronheiser, P. Hashemi, J. Kelly, J. Li, N. Loubet, P. Montanini,
VLSI Technology Symposium, IEEE, JSAP, 2016
Abstract

Vertical Slit FET at 7-nm Node and Beyond
Yang, Ping-Lin and Hook, Terence B and Oldiges, Philip J and Doris, Bruce B
IEEE Transactions on Electron Devices 63(8), 3327--3334, IEEE, 2016
Abstract

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Xie, R and Montanini, P and Akarvardar, K and Tripathi, N and Haran, B and Johnson, S and Hook, T and Hamieh, B and Corliss, D and Wang, J and others
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 2--7
Abstract

Toward Ultimate Scaling of MOSFET
Muralidhar, Ramachandran and Lauer, Isaac and Cai, Jin and Frank, David J and Oldiges, Phil
IEEE Transactions on Electron Devices 63(1), 524--526, IEEE, 2016
Abstract


2015

Hybrid methodology to model random dopant fluctuations in low doped FinFETs
Agarwal, Samarth and Johnson, Jeffrey B and Bajaj, Mohit and Furkay, Stephen S and Oldiges, Philip J and Robison, Robert R and Murali, KVRM
Journal of Computational Electronics 14(2), 533--536, Springer, 2015
Abstract

Specific contact resistivity of n-type Si and Ge MS and MIS contacts
Kim, Jiseok and Oldiges, Phillip J and Li, Hui-feng and Niimi, Hiroaki and Raymond, Mark and Zeitzoff, Peter and Kamineni, Vimal and Adusumilli, Praneet and Niu, Chengyu and Chafik, Fadoua
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on, pp. 234--237
Abstract

Total ionizing dose radiation effects on 14 nm FinFET and SOI UTBB technologies
Hughes, Harold and McMarr, Patrick and Alles, Michael and Zhang, Enxia and Arutt, Charles and Doris, Bruce and Liu, Derrick and Southwick, Richard and Oldiges, Philip
Radiation Effects Data Workshop (REDW), 2015 IEEE, pp. 1--6
Abstract

A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs
T. Yamashita, S. Mehta, V. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Zuoguang Liu, D. Lu, F. Chen, S. Khan, et. al.
2015 Symposium on VLSI Technology and Circuits (VLSI)

Super fast physics-based methodology for accurate memory yield prediction
Joshi, Rajiv V and Kim, Keunwoo and Kanj, Rouwaida and Bhoj, Ajay N and Ziegler, Matthew M and Oldiges, Phil and Kerber, Pranita and Wong, Robert and Hook, Terence and Saroop, Sudesh and others
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(3), 534--543, IEEE, 2015
Abstract

Finite element based three dimensional Schr{\"o}dinger solver for nano-scale devices
Agarwal, Samarth and Xiu, Kai and Bajaj, Mohit and Johnson, Jeffrey B and Furkay, Stephen and Oldiges, Phil and Murali, KVRM
Journal of Computational Electronics 14(1), 163--166, Springer, 2015
Abstract

SOI FinFET soft error upset susceptibility and analysis
Oldiges, Phil and Rodbell, Kenneth P and Gordon, M and Massey, John G and Stawiasz, Kevin and Murray, C and Tang, H and Kim, K and Muller, K Paul
Reliability Physics Symposium (IRPS), 2015 IEEE International, pp. 4B--2
Abstract

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
Kim, Seong-Dong and Guillorn, Michael and Lauer, Isaac and Oldiges, Phil and Hook, Terence and Na, Myung-Hee
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, pp. 1--3
Abstract


2014

Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs
Nayak, Kaushik and Agarwal, Samarth and Bajaj, Mohit and Oldiges, Philip J and Murali, Kota VRM and Rao, Valipe Ramgopal
IEEE Transactions on Electron Devices 61(11), 3892--3895, IEEE, 2014
Abstract

CMOS logic device and circuit performance of Si gate all around nanowire MOSFET
Nayak, Kaushik and Bajaj, Mohit and Konar, Aniruddha and Oldiges, Philip J and Natori, Kenji and Iwai, Hiroshi and Murali, Kota VRM and Rao, Valipe Ramgopal
IEEE Transactions on Electron Devices 61(9), 3066--3074, IEEE, 2014
Abstract

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Lu, Darsen and Morin, Pierre and Sahu, Bhagawan and Hook, Terence B and Hashemi, Pouya and Scholze, Andreas and Kim, Bomsoo and Kerber, Pranita and Khakifirooz, Ali and Oldiges, Philip and others
ECS Transactions 64(6), 337--345, The Electrochemical Society, 2014
Abstract

TDDB at low voltages: An electrochemical perspective
Muralidhar, R and Shaw, T and Chen, F and Oldiges, P and Edelstein, D and Cohen, S and Achanta, R and Bonilla, G and Bazant, M
Reliability Physics Symposium, 2014 IEEE International, pp. BD--3
Abstract

10nm FINFET technology for low power and high performance applications
D. Guo, H Shang, Kazuyuki Seo, B Haran, T Standaert, Deepika Gupta, E Alptekin, D Bae, G Bae, D Chanemougame, others
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on, pp. 1--4

Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
Cheng, K and Seo, S and Faltermeier, J and Lu, D and Standaert, T and Ok, I and Khakifirooz, A and Vega, R and Levin, T and Li, J and others
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, pp. 1--2
Abstract

Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits
Nayak, Kaushik and Bajaj, Mohit and Konar, Aniruddha and Oldiges, Philip J and Iwai, Hiroshi and Murali, KVRM and Rao, V Ramgopal
Japanese Journal of Applied Physics 53(4S), 04EC16, IOP Publishing, 2014
Abstract

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Seo, K-I and Haran, B and Gupta, D and Guo, D and Standaert, T and Xie, R and Shang, H and Alptekin, E and Bae, D-I and Bae, G and others
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, pp. 1--2
Abstract

Dielectric isolated FinFETs on bulk substrate
Lu, Darsen and Cheng, Kangguo and Morin, Pierre and Loubet, Nicolas and Hook, Terence and Guo, Dechao and Khakifirooz, Ali and Oldiges, Phil and Doris, Bruce and Rim, Ken and others
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE, pp. 1--2
Abstract

Modeling, and Experimental Measurements, of the SER Critical Charge (Qcrit) in Scaled, SOI, CMOS Devices
Rodbell, Kenneth and Oldiges, Phil and Murray, Conal and Gordon, Michael and Massey, John G and Stawiasz, Kevin and Tang, Henry
Technical Report, IBM TJ Watson Research Center Yorktown Heights United States, 2014
Abstract


2013

Investigation of fixed oxide charge and fin profile effects on bulk FinFET device characteristics
Kim, Bomsoo and Bae, Dong-Il and Zeitzoff, Peter and Sun, Xin and Standaert, Theodorus E and Tripathi, Neeraj and Scholze, Andreas and Oldiges, Philip J and Guo, Dechao and Shang, Huiling and others
IEEE Electron Device Letters 34(12), 1485--1487, IEEE, 2013
Abstract

2 nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
Ortolland, C and Jaeger, D and Mcardle, TJ and Dewan, C and Robison, RR and Zhao, K and Cai, J and Chang, P and Liu, Y and Varadarajan, V and others
2013 IEEE International Electron Devices Meeting, pp. 9--4

A comparative study of fin-last and fin-first SOI FinFETs
Darsen Lu, Josephine Chang, Michael A Guillorn, Chung-Hsun Lin, Jeffrey Johnson, Philip Oldiges, Ken Rim, Mukesh Khare, Wilfried Haensch
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on, pp. 147--150

Meeting the challenge of multiple threshold voltages in highly scaled undoped FinFETs
Muralidhar, Ramachandran and Cai, Jin and Frank, David J and Oldiges, Phil and Lu, Darsen and Lauer, Isaac
IEEE Transactions on Electron Devices 60(3), 1276--1278, IEEE, 2013
Abstract

Ab initio study of metal grain orientation-dependent work function and its impact on FinFET variability
Agarwal, Samarth and Pandey, Rajan Kumar and Johnson, Jeffrey B and Dixit, Abhisek and Bajaj, Mohit and Furkay, Stephen S and Oldiges, Phil J and Murali, KVRM
IEEE Transactions on Electron Devices 60(9), 2728--2733, IEEE, 2013
Abstract


2012

Effect of Ge on dislocation nucleation from surface imperfections in Si-Ge
Li, Z and Picu, RC and Muralidhar, R and Oldiges, P
Journal of Applied Physics 112(3), 034315, AIP, 2012
Abstract

Channel Doping Impact on FinFETs for 22nm and Beyond
CH Lin, R. Kambhampati, RJ Miller, TB Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, others
VLSI Symp. on Tech. Dig., paper 2A-3, 2012

A comparison of short-channel control in planar bulk and fully depleted devices
Muralidhar, Ramachandran and Cai, Jin and Lauer, Isaac and Chan, Kevin and Kulkarni, Pranita and Kim, Young-Hee and Ren, Zhibin and Park, Dae-Gyu and Oldiges, Phil and Shahidi, Ghavam
IEEE Electron Device Letters 33(6), 776--778, IEEE, 2012
Abstract

Investigation of the Impact of Random Dopant Fluctuation on Static Noise Margin of 22nm SRAM
Xu, Sarah Q and Xiu, Kai and Oldiges, Phil
2012 - in4.iue.tuwien.ac.at
Abstract

Simulation of phonon-induced mobility under arbitrary stress, wafer and channel orientations and its application to FinFET technology
Xiu, Kai and Oldiges, Phil
identity1, 2, 2012
Abstract


2011

Impact of substrate bias on GIDL for thin-BOX ETSOI devices
P Kulkarni, Q Liu, A Khakifirooz, Y Zhang, K Cheng, F Monsieur, P Oldiges
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 103--106

Critical analysis of 14nm device options
P. Oldiges, R. Muralidhar, P. Kulkarni, CH Lin, K. Xiu, D. Guo, M. Bajaj, N. Sathaye
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 5--8

Sub-25nm FinFET with Advanced Fin Formation and Short Channel Effect Engineering
T. Yamashita, VS Basker, T. Standaert, CC Yeh, T. Yamamoto, K. Maitra, CH Lina, J. Faltermeier, S. Kanakasabapathy, M. Wang, others
VLSI Symp. on Tech. Dig., paper 2A-2, 2011

Suppression of boron diffusion in deep submicron devices
Gribelyuk, Michael A and Oldiges, Phil and Ronsheim, Paul A and Yuan, Jun and Kimball, Leon
Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 29(6), 062201, AVS, 2011
Abstract

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
Lin, Chung-Hsun and Haensch, Wilfried and Oldiges, Phil and Wang, Hailing and Williams, Richard and Chang, Josephine and Guillorn, Michael and Bryant, Andres and Yamashita, Tenko and Standaert, Theodorus and others
VLSI Technology (VLSIT), 2011 Symposium on, pp. 16--17
Abstract


2010

Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs
Pandey, Rajan K and Murali, Kota VRM and Furkay, Stephen S and Oldiges, Philip J and Nowak, Edward J
IEEE Transactions on Electron Devices 57(9), 2098--2105, IEEE, 2010
Abstract

Intrinsic effective mobility extraction with extremely scaled gate dielectrics
Z. Liu, D. Guo, K. Xiu, W.K. Henson, P.J. Oldiges
Applied Physics Letters 97(2), 023509--023509, AIP, 2010

HOT-carrier degradation in undoped-body ETSOI FETS and SOI FINFETS
M. Wang, P. Kulkarni, K. Cheng, A. Khakifirooz, VS Basker, H. Jagannathan, C.C. Yeh, V. Paruchuri, B. Doris, H. Bu, others
Reliability Physics Symposium (IRPS), 2010 IEEE International, pp. 1099--1104

Stacked devices for SEU immune design
Oldiges, P and Rodbell, K and Ning, T and Cai, J and Heidel, D and Tang, H and Wissel, L and Gordon, M
SOI Conference (SOI), 2010 IEEE International, pp. 1--2
Abstract

Technologies to further reduce soft error susceptibility in SOI
P Oldiges, R Dennard, D Heidel, T Ning, K Rodbell, H Tang, M Gordon, L Wissel
Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1--4, 2010

Characterization of Parasitic Bipolar Transistors in 45 nm Silicon-on-Insulator Technology
Wissel, Larry and Oldiges, Phil and Guo, Dechao
IEEE Transactions on Nuclear Science 57(6), 3234--3238, IEEE, 2010
Abstract

Non-planar device architecture for 15nm node: FinFET or trigate?
C.H. Lin, J. Chang, M. Guillorn, A. Bryant, P. Oldiges, W. Haensch
SOI Conference (SOI), 2010 IEEE International, pp. 1--2


2009

On the systematic analysis of ring-delay performance using statistical behavior model
Q Liang, B Greene, S-J Han, Y Wang, Y Liang, M Cai, F Yang, K Amarnath, J Johnson, E Nowak, others
Semiconductor Device Research Symposium, 2009. ISDRS'09. International, pp. 1--2

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-$\kappa$ Metal Gate MOSFETs
Guo, Dechao and Schonenberg, Kathryn and Chen, Jie and Jaeger, Daniel and Kulkarni, Pranita and Kwon, Unoh and Liang, Yue and Liu, Joyce and Song, Liyang and Arnaud, Franck and others
MRS Online Proceedings Library Archive1194, Cambridge University Press, 2009
Abstract

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, LF Edge, A Kimball, S Kanakasabapathy, K Xiu, others
Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1--4


2008

SOI series MOSFET for embedded high voltage applications and soft-error immunity
Cai, Jin and Ning, Tak and Oldiges, Philip and Chou, Anthony and Kumar, Arvind and Rausch, Werner and Haensch, Wilfried and Shahidi, Ghavam
SOI Conference, 2008. SOI. IEEE International, pp. 21--22
Abstract

Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond
Wang, Xinlin and Shahidi, Ghavam and Oldiges, Phil and Khare, Mukesh
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on, pp. 309--312
Abstract

Design implications of single event transients in a commercial 45 nm SOI device technology
Kleinosowski, AJ and Cannon, Ethan H and Pellish, Jonathan A and Oldiges, Phil and Wissel, Larry
IEEE Transactions on Nuclear Science 55(6), 3461--3466, IEEE, 2008
Abstract

Multi-bit upsets in 65nm SOI SRAMs
Cannon, Ethan H and Gordon, Michael S and Heidel, David F and KleinOsowski, AJ and Oldiges, Phil and Rodbell, Kenneth P and Tang, Henry HK
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, pp. 195--201
Abstract

Circuit design and modeling for soft errors
KleinOsowski, A and Cannon, Ethan H and Oldiges, Phil and Wissel, Larry
IBM Journal of Research and Development 52(3), 255--263, IBM, 2008
Abstract

Alpha-particle-induced upsets in advanced CMOS circuits and technology
DF Heidel, KP Rodbell, EH Cannon, C Cabral Jr, MS Gordon, P Oldiges, HHK Tang
IBM Journal of Research and Development 52(3), 225--232, IBM Corp., 2008


2007

Impact of mobile charge on matching sensitivity in SOI analog circuits
Connell, M and Grady, M and Oldiges, P and Onsongo, D and Passaro, M and Rausch, W and Ronsheim, P and Siljenberg, D
Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI, pp. 139--142
Abstract

Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
H Zhu, B B Doris, P J Oldiges, M Ieong, M Yang, H Chen
US Patent App. 11/ ..., 2007 - Google Patents, Google Patents
US Patent App. 11/693,377

Modeling \& Simulation-Performance Analysis And Transport Modeling
Oldiges, Phil and Linton, Tom
Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 99--99
Abstract

Protecting Big Blue from Rogue Subatomic Particles
E H Cannon, A KleinOsowski, M S Gordon, D F Heidel, J Hergenrother, K P Muller, P Oldiges, C Plettner, D D Reinhardt, K P Rodbell, others
IEEE International Conference on Integrated Circuit Design and Technology, 2007, pp. 1--6

Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond
Wang, Xinlin and Bryant, Andres and Dokumaci, Omer and Oldiges, Phil and Haensch, Wilfried
Simulation of Semiconductor Processes and Devices 2007, 125--128, Springer
Abstract

Latch design techniques for mitigating single event upsets in 65 nm SOI device technology
AJ KleinOsowski, E H Cannon, M S Gordon, D F Heidel, P Oldiges, C Plettner, K P Rodbell, R D Rose, H H K Tang
IEEE Transactions on Nuclear Science 54(6 Part 1), 2021--2027, 2007

Low-energy proton-induced single-event-upsets in 65 nm node, silicon-on-insulator, latches and memory cells
K P Rodbell, D F Heidel, H H K Tang, M S Gordon, P Oldiges, C E Murray
IEEE Transactions on Nuclear Science 54(6 Part 1), 2474--2479, 2007


2006

Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
S Mukhopadhyay, K Kim, X Wang, D J Frank, P Oldiges, C Chuang, K Roy
IEEE Electron Device Letters 27(4), 284, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2006

Structure and method for manufacturing planar SOI substrate with multiple orientations
H Zhu, B B Doris, M Ieong, P J Oldiges, M Yang
US Patent App. 11/ ..., 2006 - Google Patents, Google Patents
US Patent App. 11/473,835

Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs
KL Lee, MM Frank, V Paruchuri, E Cartier, B Linder, N Bojarczuk, X Wang, J Rubino, M Steen, P Kozlowski, others
VLSI Technology, 2006, pp. 160--161

Challenges and opportunities for high performance 32 nm CMOS technology
JW Sleight, I Lauer, O Dokumaci, DM Fried, D Guo, B Haran, S Narasimha, C Sheraw, D Singh, M Steigerwalt, others
Electron Devices Meeting, 2006. IEDM'06. International, pp. 1--4

Strained SiGe/Ge Buried Channel pMOSFETs Design For High Performance Applications
Wang, Xinlin and Rim, Ken and Shang, Huiling and Koester, Steve and Oldiges, Phil and Ieong, Meikei
Device Research Conference, 2006 64th, pp. 75--76
Abstract

Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs
Wang, Xinlin and Bryant, Andres and Oldiges, Phil and Narasimha, Shreesh and Dennard, Robert and Haensch, Wilfried
Simulation of Semiconductor Processes and Devices, 2006 International Conference on, pp. 283--286
Abstract

Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices
KleinOsowski, AJ and Oldiges, Phil and Williams, Richard Q and Solomon, Paul M
IEEE Transactions on Nuclear Science 53(6), 3321--3328, IEEE, 2006
Abstract

Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells
D F Heidel, K P Rodbell, P Oldiges, M S Gordon, H H K Tang, E H Cannon, C Plettner
IEEE Transactions on Nuclear Science 53(6 Part 1), 3512--3517, 2006


2005

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
MM Frank, VK Paruchuri, V Narayanan, N Bojarczuk, B Linder, S Zafar, EA Cartier, EP Gusev, PC Jamison, KL Lee, others
VLSI Technology, 2005.(VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on, pp. 97--98

Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer Regime
Wang, Xinlin and Oldiges, Phil and Bryant, Andres and Cai, Jin and Ouyang, Qiqing and Rim, Ken
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on, pp. 239--242
Abstract


2004

On the integration of CMOS with hybrid crystal orientations
Yang, M and Chan, V and Ku, SH and Ieong, M and Shi, L and Chan, KK and Murthy, CS and Mo, RT and Yang, HS and Lehner, EA and others
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 160--161
Abstract

Hole Mobility Enhancement Modeling and Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs
Wang, Xinlin and Shang, Huiling and Oldiges, Phil and Rim, Ken and Koester, Steve and Ieong, Meikei
Simulation of Semiconductor Processes and Devices 2004, pp. 65--68, Springer
Abstract

Examination of Spatial Frequency Dependence of Line Edge Roughness on MOS Device Characteristics
Oldiges, Phil and Murthy, Cheruvu
Simulation of Semiconductor Processes and Devices 2004, pp. 239--242, Springer, Vienna
Abstract


2003

Does line-edge roughness matter?: FEOL and BEOL perspectives
Lin, Qinghuang and Black, Charles T and Detavernier, Christophe and Gignac, Lynne and Guarini, Kathryn and Herbst, Brian and Kim, Hyungjun and Oldiges, Philip and Petrillo, Karen E and Sanchez, Martha I
Microlithography 2003, pp. 1076--1085
Abstract

Gate capacitance optimization for arrays of carbon nanotube field-effect transistors
Wang, Xinlin and Wong, H-SP and Oldiges, P and Miller, RJ
Device Research Conference, 2003, pp. 87--88
Abstract

Strained Si CMOS (SS CMOS) technology: opportunities and challenges
Rim, K and Anderson, R and Boyd, D and Cardone, F and Chan, K and Chen, H and Christansen, S and Chu, J and Jenkins, K and Kanarsky, T and others
Solid-State Electronics 47(7), 1133--1139, Elsevier, 2003
Abstract

Technology modeling for emerging SOI devices
Ieong, Meikei and Oldiges, Phil
IEICE transactions on electronics 86(3), 301--307, The Institute of Electronics, Information and Communication Engineers, 2003
Abstract

Electrostatic analysis of carbon nanotube arrays
Wang, Xinlin and Wong, Hon-Sum Philip and Oldiges, Phil and Miller, Robert J
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on, pp. 163--166
Abstract


2002

Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
Cai, J and Ajmera, A and Ouyang, C and Oldiges, P and Steigerwalt, M and Stein, K and Jenkins, K and Shahidi, G and Ning, T
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on, pp. 172--173
Abstract

Soft error rate scaling for emerging SOI technology options
P Oldiges, K Bernstein, D Heidel, B Klaasen, E Cannon, R Dennard, H Tang, M Ieong, H S P Wong
Symposium on VLSI technology, pp. 46--47, 2002

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs
Ren, Zhibin and Hegde, Suri and Doris, Bruce and Oldiges, Phil and Kanarsky, Thomas and Dokumaci, Omer and Roy, Ronnen and Leong, M and Jones, Erin C and Wong, H-SP
IEEE Electron Device Letters 23(10), 609--611, IEEE, 2002
Abstract

FinFET design considerations based on 3-D simulation and analytical modeling
Pei, Gen and Kedzierski, Jakub and Oldiges, Phil and Ieong, Meikei and Kan, EC-C
IEEE Transactions on Electron Devices 49(8), 1411--1419, IEEE, 2002
Abstract

On the optimal shape and location of silicided source and drain contacts
Oldiges, Phil and Murthy, Cheruvu and Wang, Xinlin and Fung, Sam and Purtell, Robert
Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on, pp. 39--42
Abstract

A simulation study on thin SOI bipolar transistors with fully or partially depleted collector
Ouyang, Qiqing Christine and Cai, Jin and Ning, Tak and Oldiges, Phil and Johnson, Jeffery B
Bipolar/BiCMOS Circuits and Technology Meeting, 2002. Proceedings of the 2002, pp. 28--31
Abstract


2001

Threshold-voltage anomaly in sub-0.2/spl mu/m DRAM buried-channel pFET devices
Murthy, CS and Katsumata, R and Inaba, S and Rengarajan, R and Oldiges, P and Ronsheim, P
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on, pp. 19--22
Abstract

A practical approach to modeling strained silicon NMOS devices
Oldiges, Phil and Wang, Xinlin and Ieong, MeiKei and Fischer, Stephen and Rim, Ken
Simulation of Semiconductor Processes and Devices 2001, pp. 292--295, Springer
Abstract


2000

Theoretical determination of the temporal and spatial structure of/spl alpha/-particle induced electron-hole pair generation in silicon
Oldiges, Phil and Dennard, Robert and Heidel, Dave and Klaasen, Bill and Assaderaghi, Fariborz and Ieong, Meikei
IEEE Transactions on Nuclear Science 47(6), 2575--2579, IEEE, 2000
Abstract

DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS
Ieong, Meikei and Wong, H-SP and Taur, Yuan and Oldiges, Phil and Frank, David
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on, pp. 147--150
Abstract

Modeling line edge roughness effects in sub 100 nanometer gate length devices
P. Oldiges, Q. Lin, K. Petrillo, M. Sanchez, M. Ieong, M. Hargrove
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on, pp. 131--134


1999

A Model for Reverse Short Channel Effect and Capacitance-Voltage Characteristics
Zhu, Huilong and Oldiges, Phil and Khalil, Nadim
Journal of The Electrochemical Society 146(5), 1977--1983, The Electrochemical Society, 1999
Abstract


1998

Predictive Soft Error Rate Evaluation System
Oldiges, Phil and Knowlton, Brett and Flatley, Robert
Proceedings of Simulation of Semiconductor Processes and Devices (SISPAD), 392--395, 1998
Abstract


Year Unknown

Emerging CMOS devices
Guillorn, Michael A and Loubet, Nicolas J and Yeung, Chun-Wing and Chao, Robin and Muthinti, Raja and Demarest, James and Robison, Robert and Miao, Xin and Zhang, Jingyun and Hook, Terry and others
ieeexplore.ieee.org, 0
Abstract

Low Energy Proton (LEP) SEUs in 32 nm SOI SRAMs at Low Vdd.
Rodbell, Kenneth P and Gordon, Michael S and Stawiasz, Kevin G and Oldiges, Phil and Lilja, Klas and Turowski, Marek
ieeexplore.ieee.org, 0
Abstract