Phil Oldiges  Phil Oldiges photo       

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Device Design & Modeling Czar
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)  |  IEEE Nuclear and Plasma Sciences Society  |  IEEE, Senior Member  |  New York Academy of Science  |  Sigma Pi Sigma  |  Tau Beta Pi

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More information:  ResearchGate profile  |  LinkedIn profile


2017

Asymmetric finFET memory access transistor
Lam, Chung H and Lin, Chung-Hsun and Lu, Darsen D and Oldiges, Philip J
US Patent 9,553,173
Abstract


2016

Radiation tolerant device structure
Doris, Bruce B and Khakifirooz, Ali and Lu, Darsen D and Oldiges, Philip J
US Patent 9,515,171
Abstract


2015

Finfet pcm access transistor having gate-wrapped source and drain regions
Lam, Chung H and Lin, Chung-Hsun and Lu, Darsen D and Oldiges, Philip J
US Patent App. 14/832,108
Abstract

Non-uniform gate dielectric for u-shape mosfet
Kerber, Pranita and Leobandung, Effendi and Oldiges, Philip J
US Patent App. 14/626,323
Abstract

Techniques for quantifying fin-thickness variation in FINFET technology
Haensch, Wilfried EA and Lin, Chung-Hsun and Oldiges, Philip J and Rim, Kern
US Patent 8,940,558
Abstract

Method and structure for dielectric isolation in a fin field effect transistor
Wang, Yanfeng and Guo, Dechao and Lu, Darsen and Oldiges, Philip J and Wang, Gan and Wang, Xin
US Patent 9,034,715
Abstract


2014

Devices having reduced susceptibility to soft-error effects and method for fabrication
Ning, Tak H and Oldiges, Philip J
US Patent 8,642,407
Abstract

Structure for heavy ion tolerant device, method of manufacturing the same and structure thereof
Hakey, Mark C and Ning, Tak H and Oldiges, Philip J and Tang, Henry HK
US Patent 8,890,256
Abstract

Apparatus for modeling of FinFET width quantization
Haensch, Wilfried Ernest-august and Lin, Chung-Hsun and Oldiges, Philip J and Wang, Hailing and Williams, Richard Q
US Patent 8,806,419
Abstract

Methods for modeling of FinFET width quantization
Haensch, Wilfried Ernest-august and Lin, Chung-Hsun and Oldiges, Philip J and Wang, Hailing and Williams, Richard Q
US Patent 8,799,848
Abstract


2013


Thin body fet nanopore sensor for sensing and screening biomolecules
Christopher, PD and Muralidhar, Ramachandran and Oldiges, Philip J and Zafar, Sufi
US Patent App. 13/941,124
Abstract

Interface structure for channel mobility improvement in high-k metal gate stack
Chen, Tze-Chiang and Guo, Dechao and Oldiges, Philip J and Wang, Yanfeng
US Patent 8,492,852
Abstract

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers
Chidambarrao, Dureseti and Muralidhar, Ramachandran and Oldiges, Philip J and Ontalus, Viorel
US Patent 8,541,814
Abstract

Stressed channel FET with source/drain buffers
Johnson, Jeffrey B and Muralidhar, Ramachandran and Oldiges, Philip J and Ontalus, Viorel C and Xiu, Kai
US Patent 8,361,847
Abstract


2012

Stressor in planar field effect transistor device
Dechao Guo, Pranita Kulkarni, Philip J Oldiges, Alexander Reznicek, Keith Kwong Hon Wong
US Patent 8,288,217

Implant free extremely thin semiconductor devices
Kangguo Cheng, Bruce B Doris, Dechao Guo, Pranita Kulkarni, Philip J Oldiges, Ghavam G Shahidi
US Patent 8,304,301


2011

Ultra-thin semiconductor on insulator metal gate complementary field effect transistor with metal gate and method of forming thereof
Zhu, Huilong and Doris, Bruce B and Oldiges, Philip J
US Patent 7,883,944
Abstract

Method and structure for improving uniformity of passive devices in metal gate technology
Satya N Chakravarti, Dechao Guo, Wilfried Ernst-August Haensch, Pranita Kulkarni, Fei Liu, Philip J Oldiges, Keith Kwong Hon Wong
US Patent 8,053,317

Hybrid SOI/bulk semiconductor transistors
Zhu, Huilong and Oldiges, Philip J and Doris, Bruce B and Wang, Xinlin and Gluschenkov, Oleg and Chen, Huajie and Zhang, Ying
US Patent 7,923,782
Abstract

Apparatus and method for hardening latches in SOI CMOS devices
Ethan H Cannon, AJ Kleinosowski, K Paul Muller, Tak H Ning, Philip J Oldiges, Leon J Sigal, James D Warnock, Dieter Wendel
US Patent 7,888,959


2010

Anti-halo compensation
Zhu, Huilong and Oldiges, Philip and Murthy, Cheruvu S
US Patent 7,776,725
Abstract

Method of making double-gated self-aligned finFET having gates of different lengths
Zhu, Huilong and Doris, Bruce B and Wang, Xinlin and Beintner, Jochen and Zhang, Ying and Oldiges, Philip J
US Patent 7,785,944
Abstract

Structure for planar SOI substrate with multiple orientations
Zhu, Huilong and Doris, Bruce B and Ieong, Meikei and Oldiges, Philip J and Yang, Min
US Patent 7,691,482
Abstract


2009

Method for soft error modeling with double current pulse
Kleinosowski, AJ and Oldiges, Philip J and Solomon, Paul M and Williams, Richard Q
US Patent 7,627,840
Abstract


2008

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors
Aitken, John M and Cannon, Ethan H and Oldiges, Philip J and Strong, Alvin W
US Patent 7,388,274
Abstract

Hybrid SOI-bulk semiconductor transistors
Zhu, Huilong and Oldiges, Philip J and Doris, Bruce B and Wang, Xinlin and Gluschenkov, Oleg and Chen, Huajie and Zhang, Ying
US Patent 7,452,761
Abstract

Structure and method of making double-gated self-aligned finFET having gates of different lengths
Zhu, Huilong and Doris, Bruce B and Wang, Xinlin and Beintner, Jochen and Zhang, Ying and Oldiges, Philip J
US Patent 7,348,641
Abstract

MOSFET structure with ultra-low K spacer
Huang, Elbert E and Oldiges, Philip J and Shahidi, Ghavam G and Tyberg, Christy S and Wang, Xinlin and Wisnieff, Robert L
US Patent 7,365,378


2007

Hardened transistors in soi devices
Cai, Jin and Haensch, Wilfried E and Ning, Tak H and Oldiges, Philip J and Shahidi, Ghavam G
US Patent App. 11/857,569
Abstract


2006

Heater for annealing trapped charge in a semiconductor device
Aitken, John M and Cannon, Ethan H and Oldiges, Philip J and Strong, Alvin W
US Patent 7,064,414
Abstract


2005

Thin channel FET with recessed source/drains and extensions
Chen, Huajie and Doris, Bruce B and Oldiges, Philip J and Wang, Xinlin and Zhu, Huilong
US Patent 6,924,517
Abstract


2004

Damascene double-gate MOSFET structure and its fabrication method
Hanafi, Hussein Ibrahim and Jones, Erin C and Murthy, Cheruvu Suryanarayana and Oldiges, Philip Joseph and Shi, Leathen
US Patent 6,686,630
Abstract