Rasit Onur Topaloglu  Rasit Onur Topaloglu photo       

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Advisory R&D Engineer / Technical Lead

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Professional Associations

Professional Associations:  ACM  |  IEEE   |  IEEE Council on EDA  |  IEEE Mid-Hudson Section  |  SPIE -- International Society of Optical Engineering


2017

Editorial for JETC Special Issue on Alternative Computing Systems
Topaloglu, Rasit O and Verma, Naveen
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13(3), 38, ACM, 2017
Abstract

Identification and sensitivity analysis of a correlated ground rule system (design arc)
Eastman, Eric and Chidambarrao, Dureseti and Rausch, Werner and Topaloglu, Rasit O and Shao, Dongbing and Ramachandran, Ravikumar and Angyal, Matthew
SPIE Advanced Lithography, pp. 101480I--101480I, 2017
Abstract


2016

ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite
Topaloglu, Rasit O
Proceedings of the 35th International Conference on Computer-Aided Design, pp. 41, 2016
Abstract


2015

E-beam inspection throughput acceleration via Targeted Critical Area Inspection
Patterson, Oliver D and Topaloglu, Rasit O and Hafer, Richard F and Lei, Shuen-Cheng Chris and Tang, Xiaohu
2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 260--265



2014

Guest Editorial: Special Section on Optical Interconnects
Topaloglu, Rasit O
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33(6), 813--813, IEEE, 2014

Technology implications on approximate computing
Rasit O. Topaloglu
Variability Modeling and Characterization Workshop, 2014

High-performance computing for the theoretical study of nanoscale and molecular interconnects
Rasit O. Topaloglu, Swati Manjari, Saroj Nayak
Nanotechnology: Concepts, Methodologies, Tools, and Applications, IGI Global, 2014

Guest editorial: Special section on optical interconnects
Rasit O. Topaloglu
TCAD, 2014




2013

Chip-scale physical interconnect models (Tutorial)
Topaloglu, Rasit O
2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

Welcome to ISQED 2013
Budnik, Mark and Topaloglu, Rasit and Chatterjee, Pallab and Bowman, Keith and Gadepally, Kamesh and Wesling, Paul and Alam, Syed M and Joshi, Rajiv
International Symposium on Quality Electronic Design (ISQED), 2013

Interferometry-based characterization of chip-scale topography for advanced semiconductor nodes
R. O. Topaloglu, P. Vukkadala, R. Venigalla, B. J. Morgenfeld, R. Ramkhalawon, J. K. Sinha, N. Lustig, S. Greco,
International Conference on Planarization/CMP Technology, 2013

Chip-scale physical interconnect models (Tutorial)
Rasit O. Topaloglu
ACM/IEEE SLIP, 2013

Guest Editors' Introduction to Practical Parallel EDA
Rasit O. Topaloglu, Bevan Baas
IEEE Design & Test, 2013



2012

Design-technology co-optimization in next generation lithography
Zhang, Hongbo
Ph.D. Thesis, 2012
Abstract

Block-level 3D IC design with through-silicon-via planning
Kim, Dae Hyun and Topaloglu, Rasit Onur and Lim, Sung Kyu
17th Asia and South Pacific Design Automation Conference, pp. 335--340, 2012

Efficient multi-die placement for blank defect mitigation in EUV lithography
Du, Yuelin and Zhang, Hongbo and Wong, Martin DF and Deng, Yunfei and Topaloglu, Rasit O
SPIE Advanced Lithography, pp. 832231--832231, 2012

Characterization and decomposition of self-aligned quadruple patterning friendly layout
Zhang, Hongbo and Du, Yuelin and Wong, Martin DF and Topaloglu, Rasit O
SPIE Advanced Lithography, pp. 83260F--83260F, 2012


2011

Is Manufacturability with Double Patterning a Burden on Designer?: Analysis of Device and Circuit Aspects
ONUR TOPALOGLU, Rasit
Proceedings of SPIE, the International Society for Optical Engineering, 2011
Abstract

Yuelin Du, Martin DF Wong, Rasit Topaloglu, Will Conley," Effective decomposition algorithm for self-aligned double patterning lithography
Zhang, Hongbo
Proc. SPIE, 2011

Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs
Hurat, Philippe and Topaloglu, Rasit O and Nachman, Ramez and Pathak, Piyush and Condella, Jac and Madhavan, Sriram and Capodieci, Luigi
SPIE Advanced Lithography, pp. 797412--797412, 2011

Probability Propagation and Yield Optimization for Analog Circuits
Topaloglu, Rasit O and Yu, Guo and Li, Peng
Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits, 61, Bentham Science Publishers, 2011

Fast variational static IR-drop analysis on the graphical processing unit
Topaloglu, Rasit Onur
Quality Electronic Design (ISQED), 2011 12th International Symposium on, pp. 1--6

A Brief Overview of Lithographic Advancements in the Last Decade with a Focus on Double Patterning
Kye, Jongwook and Topaloglu, Rasit O
Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits, 3, Bentham Science Publishers, 2011

Is manufacturability with double patterning a burden on designer? Analyses of device and circuit aspects
Topaloglu, Rasit Onur
SPIE Advanced Lithography, pp. 79740A--79740A, 2011

GPU programming for EDA with OpenCL
Topaloglu, Rasit O and Gaster, Benedict
Proceedings of the International Conference on Computer-Aided Design, pp. 63--66, 2011

TSV density-driven global placement for 3D stacked ICs
Kim, Dae Hyun and Topaloglu, Rasit Onur and Lim, Sung Kyu
SoC Design Conference (ISOCC), 2011 International, pp. 135--138

Hot spot detection for indecomposable self-aligned double patterning layout
Zhang, Hongbo and Du, Yuelin and Wong, Martin DF and Topaloglu, Rasit O
SPIE Photomask Technology, pp. 81663E--81663E, 2011

Effective decomposition algorithm for self-aligned double patterning lithography
Zhang, Hongbo and Du, Yuelin and Wong, Martin DF and Topaloglu, Rasit and Conley, Will
SPIE Advanced Lithography, pp. 79730J--79730J, 2011

EUV mask preparation considering blank defects mitigation
Du, Yuelin and Zhang, Hongbo and Wong, Martin DF and Topaloglu, Rasit O
SPIE Photomask Technology, pp. 816611--816611, 2011

Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Zhang, Hongbo and Du, Yuelin and Wong, Martin DF and Topaloglu, Rasit
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 71--76

Applications driving 3D integration and corresponding manufacturing challenges
Topaloglu, Rasit
Proceedings of the 48th Design Automation Conference, pp. 220--223, 2011

High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects
Topaloglu, Rasit O and Manjari, Swati R and Nayak, Saroj K
Handbook of Research on Computational Science and Engineering: Theory and Practice: Theory and Practice2, 78, IGI Global, 2011

Recent topics on modeling of semiconductor processes, devices, and circuits
Topaloglu, Rasit Onur and Li, Peng
2011 - books.google.com, Bentham Science Publishers


2010

SIS wide-band model extraction methodology for SOI on-chip inductor
Topaloglu, Rasit Onur and Goo, Jung-Suk and Loke, Alvin LS and Oshima, Michael M and Sim, Sam Wonsae
2010 International Conference on Microelectronic Test Structures (ICMTS), pp. 90--93

Test structures to quantify contact placement-impacted drain current variations
Topaloglu, Rasit O and Wu, Zhi-Yuan and Icel, Ali B
2010 International Conference on Microelectronic Test Structures (ICMTS), pp. 188--191

3-2-1 contact: an experimental approach to the analysisof contacts in 45 nm and below
Topaloglu, Rasit O
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, pp. 59--66, 2010

Assessing chip-level impact of double patterning lithography
Jeong, Kwangok and Kahng, Andrew B and Topaloglu, Rasit O
Quality Electronic Design (ISQED), 2010 11th International Symposium on, pp. 122--130

Enabling 3D integration through optimal topograph
Kim, Dae Hyun and Wu, Yen-Kuan and Topaloglu, Rasit Onur and Lim, Sung Kyu
Proc. International Workshop on Design for Manufacturability and Yield Workshop, 2010


2009

A Framework for Chip-Level Evaluation of Misalignment and Linewidth Error Impacts Across Double-Patterning Technology Options
Jeong, Kwangok and Kahng, Andrew B and Topaloglu, Rasit O
International Workshop on Design for Manufacturability and Yield, 2009

CAD utilities to comprehend layout-dependent stress effects in 45 nm high-performance SOI custom macro design
Sultan, Akif and Faricelli, John and Suryagandh, Sushant and Mathur, Kaveri and Pattison, James and Hannon, Sean and Constant, Greg and Kumar, Kalyana and Carrejo, Kevin and Meier, Joe and others
2009 10th International Symposium on Quality Electronic Design, pp. 442--446

Is overlay error more important than interconnect variations in double patterning?
Jeong, Kwangok and Kahng, Andrew B and Topaloglu, Rasit O
Proceedings of the 11th international workshop on System level interconnect prediction, pp. 3--10, 2009


2008


Process variation characterization and modeling of nanoparticle interconnects for foldable electronics
Topaloglu, Rasit Onur
9th International Symposium on Quality Electronic Design (isqed 2008), pp. 498--501

DOE-based extraction of CMP, active and via fill impact on capacitances
Kahng, Andrew B and Topaloglu, Rasit Onur
IEEE Transactions on Semiconductor Manufacturing 21(1), 22--32, IEEE, 2008

Chip optimization through STI-stress-aware placement perturbations and fill insertion
Kahng, Andrew B and Sharma, Puneet and Topaloglu, Rasit Onur
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(7), 1241--1252, IEEE, 2008


2007

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
Kahng, Andrew B and Topaloglu, Rasit Onur
2006 International Conference on Computer Design, pp. 222--229, 2007

Process variation-aware multiple-fault diagnosis of thermometer-coded current-steering DACs
Topaloglu, Rasit Onur
IEEE Transactions on Circuits and Systems II: Express Briefs 54(2), 191--195, IEEE, 2007

Performance-aware CMP fill pattern optimization
Kahng, Andrew B and Topaloglu, Rasit Onur
Invited Paper, in Proc. VMIC, 2007

Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization
Topaloglu, Rasit Onur
2007 IEEE Custom Integrated Circuits Conference, pp. 619--622

Exploiting STI stress for performance
Kahng, Andrew B and Sharma, Puneet and Topaloglu, Rasit O
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 83--90


2006

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.
Topaloglu, Rasit Onur and Kahng, Andrew B
ICCD, pp. 222--229, 2006

Statistical Compact Modeling and Si Verification Methodology
Wason, Vineet and An, Judy and Goo, Jung-Suk and Wu, Zhi-Yuan and Chen, Qiang and Thuruthiyil, Ciby and Topaloglu, Rasit and Chiney, Priyanka and Ali, Icel
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp. 1198--1201

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.
Topaloglu, Rasit Onur and Kahng, Andrew B
ICCD, pp. 222--229, 2006

Monte carlo-alternative probabilistic simulations for analog systems
Topaloglu, Rasit Onur
Proceedings of the 7th International Symposium on Quality Electronic Design, pp. 249--253, 2006

Generation of design guarantees for interconnect matching
Kahng, Andrew B and Topaloglu, Rasit Onur
Proceedings of the 2006 international workshop on System-level interconnect prediction, pp. 29--34



2005

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs
Topaloglu, Rasit Onur and Orailoglu, Alex
Proceedings of the 42nd annual Design Automation Conference, pp. 851--856, 2005

Forward discrete probability propagation method for device performance characterization under process variations
Topaloglu, Rasit Onur and Orailoglu, Alex
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., pp. 220--223


2004

Development of First Order Sensitivity Functions for Mismatch
Topaloglu, Rasit Onur and Orailoglu, Alex
SRC Publication P009752, 2004

On mismatch in the deep sub-micron era-from physics to circuits
Topaloglu, Rasit Onur and Orailoglu, Alex
Proceedings of the 2004 Asia and South Pacific Design Automation Conference, pp. 62--67

New current--mode special function continuous-time active filters employing only OTAs and OPAMPs
Erdogan, Erdem Serkan and Topaloglu, Rasit onur and Kuntman, Hakan and Cicekoglu*, Oguzhan
International Journal of Electronics 91(6), 345--359, Taylor & Francis, 2004


2003

Current-input current-output notch and bandpass analog filter structures as alternatives to active-R circuits
Topaloglu, Rasit Onur and Kuntman, Hakan and Cicekoglu, Oguzhan
Frequenz 57(5-6), 123--127, 2003


Year Unknown

Proper Timing and Reliability Characterization, Extraction and Optimization of CMP and Via Fills
Topaloglu, Rasit Onur
RO Topaloglu, 0

NOVEL NOTCH AND BANDPASS FILTER STRUCTURES USING OTAS AND OPAMPS
Topaloglu, Rasit Onur and Kuntman, Hakan and Cicekoglu, Oguzhan
emo.org.tr, 0


General Chair Mustafa Ozdal Intel, USA
Topaloglu, Rasit O and Lim, Sung Kyu and Taskin, Baris and Ho, Tsung-Yi and Li, Zhuo and Alpert, Chuck and Cheng, Chung-Kuan and De Michelli, Giovanni and Kahng, Andrew B and Kishinevsky, Michael
ieeexplore.ieee.org, 0