Phillip J. Restle  Phillip J. Restle photo       

contact information

Distinguished-RSM: Clocking & Power-Noise Mitigation for IBM Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash2697

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Professional Associations

Professional Associations:  IBM Academy of Technology  |  IEEE, Senior Member


2016

Distributed phase detection for clock synchronization in multi-layer 3D stacks
Liu, Yong and Pang, Liang-Teck and Restle, Phillip J
US Patent 9,231,603
Abstract

Infrastructure for performance based chip-to-chip stacking
Carpenter, Gary Dale and Drake, Alan James and Kursun, Eren and Restle, Phillip John
US Patent 9,251,913
Abstract

Stitchable global clock for 3D chips
Franch, Robert L and Kursun, Eren and Pang, Liang-Teck and Restle, Phillip J
US Patent 9,348,357
Abstract

Clock skew analysis and optimization
Restle, Phillip J and Warnock, James D
US Patent 9,494,968
Abstract


2015

Wide bandwidth resonant global clock distribution
Bucelot, Thomas J and Drake, Alan J and Groves, Robert A and Hibbeler, Jason D and Kim, Yong I and Pang, Liang-Teck and Reohr, William R and Restle, Phillip J and Thomson, Michael GR
US Patent 9,054,682
Abstract

Tunable sector buffer for wide bandwidth resonant global clock distribution
Bucelot, Thomas J and Drake, Alan J and Groves, Robert A and Hibbeler, Jason D and Kim, Yong I and Pang, Liang-Teck and Reohr, William R and Restle, Phillip J and Thomson, Michael GR
US Patent 9,058,130
Abstract

Clock buffers with pulse drive capability for power efficiency
Bansal, Aditya and Bucelot, Thomas J and Drake, Alan J and Restle, Phillip J and Shan, David W and Sharad, Mrigank
US Patent App. 14/973,363
Abstract


2014

Designing a robust power efficient clock distribution network
Alpert, Charles Jay and Kozhaya, Joseph Nicolas and Li, Zhuo and Palumbo, Joseph J and Qian, Haifeng and Restle, Phillip John and Sze, Chin Ngai and Zhou, Ying
US Patent 8,677,305
Abstract

Changing resonant clock modes
Bucelot, Thomas J and Drake, Alan and Friedrich, Joshua D and Hibbeler, Jason D and Pang, Liang-Teck and Reohr, William R and Restle, Phillip John and Still, Gregory S and Thomson, Michael GR
US Patent 8,736,342
Abstract

Defect detection on characteristically capacitive circuit nodes
Pang, Liang-Teck and Reohr, William Robert and Restle, Phillip John
US Patent 8,860,425
Abstract

Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints
Kozhaya, Joseph N and Restle, Phillip J and Shan, David Wen-Hao
US Patent 8,863,066
Abstract

Setting switch size and transition pattern in a resonant clock distribution system
Hibbeler, Jason D and Reohr, William R and Restle, Phillip J
US Patent 8,850,373
Abstract


2013

Vertical power budgeting and shifting for three-dimensional integration
Bose, Pradip and Carpenter, Gary D and Floyd, Michael S and Kursun, Eren and Restle, Phillip J and Scheuermann, Michael R
US Patent 8,516,426
Abstract

VERTICAL POWER BUDGETING AND SHIFTING FOR 3D INTEGRATION
Pradip Bose, Gary D Carpenter, Michael S Floyd, Eren Kursun, Phillip J Restle, Michael R Scheuermann
US Patent 20,130,055,185



2011

Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique
Hwang, Charlie Chornglii and Neves, Jose Correia and Restle, Phillip John
US Patent 7,941,689
Abstract




2010

Hindering Side-Channel Attacks in Integrated Circuits
Gary D Carpenter, Eren Kursun, Phillip J Restle, Michael R Scheuermann
US Patent App. 12/945,155


2009



2008

Hierarchical scalable high resolution digital programmable delay circuit
Hwang, Charlie C and Restle, Phillip J and Sigal, Leon J
US Patent 7,456,671
Abstract

Built in self test circuit for measuring total timing uncertainty in a digital data path
Robert L Franch, William V Huott, Norman K James, Phillip J Restle, Timothy M Skergan, others
US Patent 7,400,555

METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH
Robert L Franch, William V Huott, Norman K James, Phillip J Restle, Timothy M Skergan
US Patent App. 12/045,053

DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE
Robert L Franch, William V Huott, Norman K James, Phillip J Restle, Timothy M Skergan
US Patent App. 12/045,059


2006

System and method for derivative-free optimization of electrical circuits
Walker, Steven G and Visweswariah, Chandramouli and Scheinberg, Katya and Restle, Phillip
US Patent 7,117,455
Abstract

Method and apparatus for correcting duty cycle error in a clock distribution network
Charlie Chornglii Hwang, Phillip John Restle, Michael George Robert Thomson
US Patent App. 11/339,124


2005



2003

Alpha particle shield for integrated circuit
Richard A Wachnik, Henry A Nye III, Charles R Davis, Theodore H Zabel, Phillip J Restle
US Patent 6,531,759


2002

Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
Allan H Dansky, Alina Deutsch, Gerard V Kopcsay, Phillip J Restle, Howard H Smith, others
US Patent 6,418,401

System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation
Allan Harvey Dansky, Alina Deutsch, Gerard Vincent Kopcsay, Phillip John Restle, Howard Harold Smith, others
US Patent 6,342,823


2001

XY grid tree tuning method
Peter J Camporese, Alina Deutsch, Timothy Gerard McNamara, Phillip John Restle, David Allan Webber
US Patent 6,205,571

XY grid tree clock distribution network with tunable tree and grid networks
Peter J Camporese, Alina Deutsch, Timothy Gerard McNamara, Phillip John Restle, David Allan Webber
US Patent 6,311,313


1999



1997

Capacitive bend sensor
James S Neely, Phillip J Restle
US Patent 5,610,528