Valentina Salapura  Valentina Salapura photo       

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Master Inventor; Cloud Computing
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  ACM  |  ACM Distinguished Speaker   |  Fellow, IEEE  |  IEEE   |  IEEE Computer Society  |  IFIP WG 10.3

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More information:  Career Workshop for Women and Minorities in Computer Architecture


2017

Cognitive alert control framework for mobile devices
Gschwind, Michael Karl and Salapura, Valentina
US Patent 9,602,653

Music practice feedback system, method, and recording medium
Kim, Minkyong and Pickover, Clifford A and Salapura, Valentina
US Patent 9,672,799
Abstract

Caller protected stack return address in a hardware managed stack architecture
Duvalsaint, Karl J and Gschwind, Michael K and Salapura, Valentina
US Patent 9,606,855
Abstract

Visual comparisons using personal objects
Kim, Minkyong and Li, Min and Pickover, Clifford A and Salapura, Valentina
US Patent App. 15/587,434
Abstract

Memory access request for a memory protocol
FY Busaba and HW Cain III and MK Gschwind and V Salapura and TJ Slegel
US Patent 9,535,608

SYSTEM AND METHOD FOR INTERPRETING INTERPERSONAL COMMUNICATION
Gil, Dario and Kozhaya, Joseph N and Melville, David O and Salapura, Valentina
US Patent 20,170,004,356
Abstract

Instruction to cancel outstanding cache prefetches
Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K
US Patent 9,535,696
Abstract

Interprocessor memory status communication
Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-lung K and Slegel, Timothy J
US Patent 9,563,467
Abstract


2016

Inducing transactional aborts in other processing threads
Busaba, Fadi Y and Salapura, Valentina and Shum, Chung-Lung K
US Patent 9,513,960
Abstract

Salvaging hardware transactions with instructions to transfer transaction execution control
Cain III, Harold W and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Shum, Chung-Lung K
US Patent 9,442,775
Abstract

Automatic security parameter management and renewal
Kundu, Ashish and Mahindru, Ruchi and Mohindra, Ajay and Salapura, Valentina and Viswanathan, Mahesh
US Patent 9,325,703
Abstract

Suppressing aborting a transaction beyond a threshold execution duration based on the predicted duration
Bradbury, Jonathan D and Cain III, Harold W and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Shum, Chung-Lung K and Slegel, Timothy J
US Patent 9,430,273
Abstract

Adaptive process for data sharing with selection of lock elision and locking
Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Shum, Chung-Lung K
US Patent 9,524,195
Abstract

Prefetching of discontiguous storage locations in anticipation of transactional execution
Busaba, Fadi Y and Greiner, Dan F and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Slegel, Timothy J
US Patent 9,336,047
Abstract

Identification and verification of factual assertions in natural language
Gaucher, Brian P and Gil, Dario and Kephart, Jeffrey O and Lenchner, Jonathan and Melville, David OS and Prager, John M and Salapura, Valentina
US Patent 9,483,582
Abstract

Embedding global and collective in a torus network with message class map based tree path selection
Chen, Dong and Coteus, Paul W and Eisley, Noel A and Gara, Alan and Heidelberger, Philip and Senger, Robert M and Salapura, Valentina and Steinmacher-Burow, Burkhard and Sugawara, Yutaka and Takken, Todd E and others
US Patent 9,374,414
Abstract

Adaptive process for data sharing with selection of lock elision and locking
Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Shum, Chung-Lung K
US Patent 9,524,196
Abstract

Branch-free condition evaluation
MK Gschwind, V Salapura
US Patent 9,411,589

Branch predictor suppressing branch prediction of previously executed branch instructions in a transactional execution environment
MK Gschwind, V Salapura, CL Shum
US Patent 9,477,469

Dynamic prediction of concurrent hardware transactions resource requirements and allocation
FY Busaba, DF Greiner, MK Gschwind, MM Michael, V Salapura, CLK Shum
US Patent 9,471,371

Diagnostics for transactional execution errors in reliable transactions
MK Gschwind, V Salapura
US Patent 9,460,020

Identification and verification of factual assertions in natural language
BP Gaucher, D Gil, JO Kephart, J Lenchner, DOS Melville, JM Prager, V Salapura
US Patent 9,483,582

Collecting memory operand access characteristics during transactional execution
DF Greiner, MK Gschwind, V Salapura, TJ Slegel
US Patent 9,448,939

Salvaging hardware transactions with instructions to transfer transaction execution control
HW Cain, MK Gschwind, MM Michael, V Salapura, CLK Shum
US Patent 9,442,776

Salvaging lock elision transactions with instructions to change execution type
HW Cain, MK Gschwind, MM Michael, V Salapura, CLK Shum
US Patent 9,442,853

Using transactional execution for reliability and recovery of transient failures
MK Gschwind, V Salapura
US Patent 9,317,379

Salvaging hardware transactions with instructions
FY Busaba, HW Cain, MM Michael, V Salapura, EM Schwarz
US Patent 9,311,178

Power reduction in server memory system
DM Daly, T Karkhanis, V Salapura
US Patent 9,311,228

Reliable transactional execution using digests
M Gschwind, V Salapura
US Patent 9,292,289

Software Enabled and Disabled Coalescing of Memory Transactions
F Busaba, M Gschwind, V Salapura, CL Shum
US Patent 9,292,337

Multi-Granular Cache Management in Multi-Processor Computing Environments
F Busaba, H Cain, M Gschwind, M Michael, V Salapura, E Schwarz, CL Shum
US Patent 9,292,444

Methods and apparatus for virtual machine recovery
V Salapura, RE Harper, KD Ryu
US Patent 9,170,888

Transactional processing based upon run-time conditions
MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum
US Patent 9,262,343

Salvaging hardware transactions
HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz
US Patent 9,244,782


2015

Centralized management of high-contention cache lines in multi-processor computing environments
FY Busaba, HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum
US Patent 9,086,974

Ticket consolidation for multi-tiered applications
R Mahindru, V Salapura
US Patent 9,098,408

Coalescing memory transactions
F Busaba, M Gschwind, M Michael, V Salapura, CL Shum
US Patent 9,146,774

Scheduler for multiprocessor system switch with selective pairing
A Gara, MK Gschwind, V Salapura
US Patent 8,930,752

Mechanism for optimized intra-die inter-nodelet messaging communication
AR Mamidala, V Salapura, RW Wisniewski
US Patent 8,943,516

Ticket consolidation
MK Gschwind, R Mahindru, V Salapura
US Patent 8,972,788

Multi-node system networks with optical switches
M McGlashan-Powell, V Salapura
US Patent 8,977,124

Mixed precision estimate instruction computing narrow precision result for wide precision inputs
MK Gschwind, V Salapura
US Patent 8,984,042

Mechanisms for efficient intra-die/intra-chip collective messaging
AR Mamidala, V Salapura, RW Wisniewski
US Patent 8,990,514

Hardware enabled performance counters with support for operating system context switching
V Salapura, RW Wisniewski
US Patent 9,069,891


2014

Embedded Global Barrier and Collective in Torus Network with each Node Combining Input from Receivers According to Class Map for Output to Senders
Dong Chen, Philip Heidelberger, Noel A Eisley, Burkhard Steinmacher-Burow, Robert M Senger, Paul Coteus, Valentina Salapura, Yutaka Sugawara, Todd Takken
US Patent 8,521,990

BGQ_71 : Implementing Asynchronous Collective Operations in a Multi-Node Processing System
Sameer Kumar, Philip Heidelberger, Burkhard Steinmacher-Burow, Dong Chen, Noel A Eisley, Valentina Salapura
US Patent 8,782,164

Handling consolidated tickets
John A Bivens, Valentina Salapura
US Patent 8,781,865






METHOD AND APPARATUS FOR EFFICIENTLY TRACKING QUEUE ENTRIES RELATIVE TO A TIMESTAMP
Matthias A Blumrich, Dong Chen, Alan G Gara, Mark E Giampapa, Philip Heidelberger, Martin Ohmacht, Valentina Salapura, Pavlos Vranas
US Patent 8,756,350



2013



Quality of records containing service data
John A Bivens, Valentina Salapura, Maja Vukovic
Patent 8489441
US Patent 8,478,624




Branch-Free Condition Evaluation
Michael K Gschwind, Valentina Salapura
US Patent App. 14/081,480

Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders
Dong Chen, Paul W Coteus, Noel A Eisley, Alan Gara, Philip Heidelberger, Robert M Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E Takken, others
US Patent 8,521,990

MAINTAINING OPERAND LIVENESS INFORMATION IN A COMPUTER SYSTEM
Michael GSCHWIND, Valentina SALAPURA
WO Patent App. 13/050,901

Exploiting an Architected List-Use Operand Indication in a Computer System Operand Resource Pool
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,365

Computer Instructions for Activating and Deactivating Operands
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,363

Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,368

Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,364

Scalable Decode-Time Instruction Sequence Optimization of Dependent Instructions
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,361

Tracking operand liveliness information in a computer system and performance function based on the liveliness information
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,367

Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information
Michael K Gschwind, Valentina Salapura
US Patent App. 13/086,362

FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY
Michael K Gschwind, Brett Olsson, Valentina Salapura
US Patent App. 13/080,745

METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM
Valentina Salapura, Robert W Wisniewski
US Patent App. 13/013,891

Using DMA for copying performance counter data to memory
Alan Gara, Valentina Salapura, Robert W Wisniewski
US Patent 8,621,167


2012

Methods and apparatus for virtual machine recovery
Valentina Salapura, Richard E Harper, Kyung D Ryu
US Patent App. 13/493,304


Power reduction in server memory system
David M Daly, Tejas Karkhanis, Valentina Salapura
US Patent App. 13/439,457

Multi-node system networks with optical switches
Maurice McGlashan-Powell, Valentine Salapura
US Patent App. 13/597,763

Instruction merging optimization
Michael K Gschwind, Valentina Salapura
US Patent App. 13/432,537


HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST RECONFIGURATION OF PERFORMANCE COUNTERS
Valentina Salapura, Robert W Wisniewski
US Patent App. 12/311,316

Snoop filtering system in a multiprocessor system
Matthias Blumrich, Dong Chen, Alan Gara, Mark Giampapa, Philip Heidelberger, Dirk Hoenicke, Martin Ohmacht, Valentina Salapura, Pavlos Vranas
Patent US8103836

NOVEL SNOOP FILTER FOR FILTERING SNOOP REQUESTS
Matthias Blumrich, Dong Chen, Alan Gara, Mark Giampapa, Philip Heidelberger, Dirk Hoenicke, Martin Ohmacht, Valentina Salapura, Pavlos Vranas
US Patent App. 12/311,272

Method and apparatus of prefetching streams of varying prefetch depth
Alan Gara, Martin Ohmacht, Valentina Salapura, Krishnan Sugavanam, Dirk Hoenicke
Patent US8103832

SHARED PERFORMANCE MONITOR IN A MULTIPROCESSOR SYSTEM
George Chiu, Alan Gara, Valentina Salapura
US Patent App. 12/304,020


2011



Multi-petascale highly efficient parallel supercomputer
Sameh Asaad, Ralph Bellofatto, Michael Blocksome, Matthias Blumrich, Peter Boyle, Jose R Brunheroto, Dong Chen, Chen-Yong Cher, George L Chiu, Norman Christ, others
US Patent App. 13/004,007


Method and system of efficient packet reordering
C. Georgiou, V. Salapura
Patent US7957288




HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY
Alan GARA, Valentina SALAPURA, Robert W WISNIEWSKI
WO Patent App. 11/084,205


Single chip protocol converter
Christos J Georgiou, Victor L Gregurick, Indira Nair, Valentina Salapura, others
Patent US8036243


Method and apparatus for filtering snoop requests using a scoreboard
Matthias A Blumrich, Alan G Gara, Thomas R Puzak, Valentina Salapura
Patent US8015364


2010




Vector Loads from Scattered Memory Locations
Alexandre E Eichenberger, Michael K Gschwind, Valentina Salapura
US Patent App. 12/876,432

Ultrascalable petaflop parallel supercomputer
Matthias A Blumrich, Dong Chen, George Chiu, Thomas M Cipolla, Paul W Coteus, Alan G Gara, Mark E Giampapa, Shawn Hall, Rudolf A Haring, Philip Heidelberger, others
Patent US7761687


SYSTEM AND METHOD FOR PROCESSING REGULAR EXPRESSIONS USING SIMD AND PARALLEL STREAMS
Gregory F Russell, Valentina Salapura, Daniele P Scarpazza
US Patent App. 12/795,874



VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR
Tejas Karkhanis, Jose E Moreira, Valentina Salapura
US Patent App. 12/825,328

System and method for programmable bank selection for banked memory subsystems
Matthias A Blumrich, Dong Chen, Alan G Gara, Mark E Giampapa, Dirk Hoenicke, Martin Ohmacht, Valentina Salapura, Krishnan Sugavanam, others
Patent US7793038

SUPPORT FOR NON-LOCKING PARALLEL RECEPTION OF PACKETS BELONGING TO THE SAME RECEPTION FIFO
D Chen, P Heidelberger, V Salapura, R M Senger, B Steinmacher-Burow, Y Sugawara
US Patent App. 12/688,747


Distributed parallel messaging for multiprocessor systems
Dong Chen, Philip Heidelberger, Valentina Salapura, Robert M Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
US Patent App. 12/693,972

Multiple node remote messaging
Matthias A Blumrich, Dong Chen, Alan G Gara, Mark E Giampapa, Philip Heidelberger, Martin Ohmacht, Valentina Salapura, Burkhard Steinmacher-Burow, Pavlos Vranas, others
US Patent 7,788,334


IMPLEMENTING ASYNCRONOUS COLLECTIVE OPERATIONS IN A MULTI-NODE PROCESSING SYSTEM
Dong Chen, Noel A Eisley, Philp Heidelberger, Sameet Kumar, Valentina Salapura
US Patent App. 12/697,043

Space and power efficient hybrid counters array
Alan G Gara, Valentina Salapura, others
US Patent 7,688,931


Embedding Global Barrier and Collective in a Torus Network
Dong Chen, Paul W Coteus, Noel A Eisley, Alan Gara, Philip Heidleberger, Robert M Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E Takken
US Patent App. 12/723,277


2009

Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture
Matthias A Blumrich, Dong Chen, Alan G Gara, Mark E Giampapa, Philip Heidelberger, Dirk I Hoenicke, Martin Ohmacht, Valentina Salapura, Pavlos M Vranas, others
US Patent 7,603,523


Method and system of efficient packet reordering
C. Georgiou, V. Salapura
Patent US7477644

Method and apparatus for filtering snoop requests using mulitiple snoop caches
Matthias A Blumrich, Alan G Gara, Mark E Giampapa, Martin Ohmacht, Valentina Salapura, others
US Patent 7,617,366


2008

Method and apparatus for filtering snoop requests using multiple snoop caches
Matthias A Blumrich, Alan G Gara, Valentina Salapura, others
US Patent 7,386,685

Method and apparatus for detecting a cache wrap condition
Matthias A Blumrich, Alan G Gara, Mark E Giampapa, Martin Ohmacht, Valentina Salapura, others
US Patent 7,386,684

Snoop filter for filtering snoop requests
Matthias A Blumrich, Dong Chen, Alan G Gara, Mark E Giampapa, Philip Heidelberger, Dirk I Hoenicke, Martin Ohmacht, Valentina Salapura, Pavlos M Vranas
US Patent Application 7,373,462

Low latency counter event indication
Alan G Gara, Valentina Salapura, others
US Patent 7,426,253






2007








2006


A SINGLE CHIP PROTOCOL CONVERTER
Christos J Georgiou, Victor L Gregurick, Indira Nair, Valentina Salapura, others
EP Patent 1,654,669


Programmable network protocol handler architecture
Christos J Georgiou, Monty M Denneau, Valentina Salapura, Robert M Bunce
US Patent 7,072,970



2005


Method and system for data-driven runtime alignment operation
Alexandre E Eichenberger, Michael Gschwind, Valentina Salapura, Peng Wu
US Patent App. 11/176,988




2004

Pipelined packet processing
Robert Michael Bunce, Christos John Georgiou, Valentina Salapura
US Patent 6,836,808


2003

SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN
Christos J Georgiou, Victor L Gregurick, Valentina Salapura
US Patent App. 10/604,491



2002

Method and apparatus for prioritized instruction issue queue
M K Gschwind, V Salapura
US Patent App. 20,030/163,671


2001

Programmable storage network protocol handler architecture
C J Georgiou, M M Denneau, V Salapura, R M Bunce
US Patent App. 20,030/067,913

Configurable memory array
Michael K Gschwind, Valentina Salapura
US Patent App. 09/940,709