Jun Sawada  Jun Sawada photo       

contact information

RSM Brain-Inspired Computing Hardware Design
IBM Almaden Research Center
  +1dash512dash286dash8410

links

Professional Associations

Professional Associations:  IEEE


2016

Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications
Jun Sawada, Filipp Akopyan, Andrew S. Cassidy, Brian Taba, Michael V. DeBole, Pallab Datta, Rodrigo Alvarez-Icaza, Arnon Amir, John V. Arthur, Alexander Andreopoulos, Rathinakumar Appuswamy, Heinz Baier, Davis Barch, David J. Berg, Carmelo di Nolfo, Steve
Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2016, Salt Lake City, UT, USA, November 13-18, 2016, pp. 12


2015

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L
IEEE Trans. on CAD of Integrated Circuits and Systems 34(10), 1537--1557, 2015


2014

A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernard Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron
Science 345(6197), 668--673, American Association for the Advancement of Science, 2014

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with 100 Speedup in Time-to-Solution and 100, 000 Reduction in Energy-to-Solution
Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc Gonz\'{a}lez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Hayme
International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2014, New Orleans, LA, USA, November 16-21, 2014, pp. 27--38


2013

Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
Andrew S. Cassidy, Paul Merolla, John V. Arthur, Steven K. Esser, Bryan L. Jackson, Rodrigo Alvarez-Icaza, Pallab Datta, Jun Sawada, Theodore M. Wong, Vitaly Feldman, Arnon Amir, Daniel Ben Dayan Rubin, Filipp Akopyan, Emmett McQuinn, William P. Risk, Dha
The 2013 International Joint Conference on Neural Networks, IJCNN 2013, Dallas, TX, USA, August 4-9, 2013, pp. 1--10


2011

Hybrid verification of a hardware modular reduction engine
Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael Case, Hari Mony
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, pp. 207--214, 2011


2010

Automatic verification of estimate functions with polynomials of bounded functions
Jun Sawada
Formal Methods in Computer-Aided Design (FMCAD), 2010, pp. 151--158


2009

Scalable conditional equivalence checking: An automated invariant-generation based approach
Jason Baumgartner, Hari Mony, Michael Case, Jun Sawada, Karen Yorav
Formal Methods in Computer-Aided Design, 2009. FMCAD 2009, pp. 120--127


2007

A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS
Leland Chang, Y Nakamura, RK Montoye, J Sawada, AK Martin, K Kinoshita, FH Gebara, KB Agarwal, DJ Acharyya, W Haensch, others
VLSI Circuits, 2007 IEEE Symposium on, pp. 252--253


2006

Design of shifting and permutation units using LSDL circuit family
Ramyanshu Datta, Robert Montoye, Kevin Nowka, Jun Sawada, Jacob A Abraham
Signals, Systems and Computers, 2006. ACSSC'06. Fortieth Asilomar Conference on, pp. 1692--1696

ACL2SIX: A hint used to integrate a theorem prover and an automated verification tool
Jun Sawada, Erik Reeber
Formal Methods in Computer Aided Design, 2006. FMCAD'06, pp. 161--170

Combining ACL2 and an automated verification tool to verify a multiplier
Erik Reeber, Jun Sawada
Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications, pp. 63--70, 2006

Limited switch dynamic logic circuits for high-speed low-power circuit design
Wendy Belluomini, Damir Jamsek, Andrew K Martin, Chandler McDowell, Robert K Montoye, Hung C Ngo, Jun Sawada
IBM journal of research and development 50(2.3), 277--286, IBM, 2006


2005

An 8GHz floating-point multiply
WENDY Belluomini, DAMIR Jamsek, Andrew Martin, Chandler McDowell, Robert Montoye, Tuyet Nguyen, Hung Ngo, Jun Sawada, Ivan Vo, Ramyanshu Datta
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, pp. 374--604


2004

ACL2VHDL Translator: A Simple Approach to Fill the Semantic Gap
Jun Sawada
Proceedings of the Fifth International Workshop of the ACL2 Theorem Prover and its Applications (ACL2-2004)


2003

A double precision floating point multiply
Robert Montoye, Wendy Belluomini, Hung Ngo, Chandler McDowell, Jun Sawada, Tuyet Nguyen, Brian Veraa, James Wagoner, Mike Lee
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, pp. 336--337


2002


Mechanical verification of a square root algorithm using Taylor’s theorem
Jun Sawada, Ruben Gamboa
Formal Methods in Computer-Aided Design, pp. 274--291, 2002



2001

Derivation of a rotator circuit with homogeneous interconnect
H Peter Hofstee, Jun Sawada
Information processing letters 77(2), 131--135, Elsevier, 2001


2000

Hardware modeling using function encapsulation
Jun Sawada, Warren A Hunt Jr
Formal Methods in Computer-Aided Design, pp. 271--282, 2000


1999

Decomposing the Verification of Pipelined Microprocessors with Invariant Conditions
Jun Sawada, Warren A Hunt Jr
See URL http://www. cs. utexas. edu/users/sawada/publication/-decomp. ps, Citeseer, 1999

Results of the verification of a complex pipelined machine model
Jun Sawada, Warren A Hunt Jr
Correct Hardware Design and Verification Methods, pp. 313--316, Springer, 1999

Verifying the FM9801 microarchitecture
Warren A Hunt Jr, Jun Sawada
Micro, IEEE 19(3), 47--55, IEEE, 1999


1998

Processor verification with precise exceptions and speculative execution
Jun Sawada, Warren A Hunt Jr
Computer Aided Verification, pp. 135--146, 1998


Year Unknown

ISSCC 2003/SESSION 19/PROCESSOR BUILDING BLOCKS/PAPER 19.2
Robert Montoye, Wendy Belluomini, Hung Ngo, Chandler McDowell, Jun Sawada, Tuyet Nguyen, Brian Veraa, James Wagoner, Mike Lee
R Montoye, W Belluomini, H Ngo, C McDowell..., 0




Projects and Groups


Technical Areas